# Senior Engineer - Mixed-Signal Design

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: senior
**Job type**: full-time
**Salary**: $168,000 - $264,500 (Level 4) or $196,000 - $310,500 (Level 5)
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Mixed-Signal-Design-Engineer_JR2029679?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/senior-engineer-mixed-signal-design-9405b921-37a/

## Description

Join NVIDIA's Mixed-Signal high-speed I/O SerDes group as a senior engineer and work on groundbreaking technology that enables and accelerates gaming, artificial intelligence, deep learning, and autonomous driving.

As a member of this dynamic team, you'll be working with state-of-the-art technology and helping to move the needle in the industry. Your design will be consumed by standard as well as industry-leading proprietary high-speed protocols, and will serve as one of the key IPs in many complex SoC.

**Responsibilities:**

- Work with analog designers to create accurate systemVerilog models of analog components such as closed-loop PLL, Rx CTLE, SAR ADC, and optics components.

- Collaborate with system architects and digital designers to define and verify system architecture specifications and refine adaptation algorithms.

- Help streamline workflows with proper scripts to increase efficiency and enable reusability.

- Be actively involved in silicon bring-up, build scripts for debug, QA, characterization, and ATE.

**Requirements:**

- B.S. or M.S. degree in Electrical Engineering or equivalent experience.

- 6+ years of experience working in high-speed I/O digital design, with knowledge at the protocol level (SATA, PCIE, USB) preferred.

- Deep understanding of Verilog or SystemVerilog, logic design, and circuit modeling for mixed-signal blocks.

- Strong background in high-speed Serdes/PLL analog circuit design.

- Proven experience with custom digital circuit design and adaptation algorithms, such as DFE, CTLE, CDR, and offset cancellation.

- Strong background in Perl and Python scripting.

- FPGA emulation experience is a plus.

**Benefits:**

- Base salary: $168,000 - $264,500 (Level 4) or $196,000 - $310,500 (Level 5).

- Equity and benefits package.

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## Skills

### Required
- Electrical Engineering
- SystemVerilog
- Verilog
- high-speed I/O digital design
- Serdes/PLL analog circuit design
- Perl
- Python
- custom digital circuit design

### Nice to have
- FPGA emulation

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