# SOC Engineering, Sr Engineer **Company**: Synopsys **Location**: Bengaluru, Karnataka **Work arrangement**: onsite **Experience**: senior **Job type**: full-time **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/bengaluru/soc-engineering-sr-engineer/44408/98213725744?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_9401f972-3e5 ## Description Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place & route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. **What You'll Be Doing:** - Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs. - Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets. - Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities. - Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence. - Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions. - Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency. - Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed. **The Impact You Will Have:** - Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide. - Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations. - Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys. - Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise. - Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction. - Support strategic customer engagements and help expand Synopsys' presence in the semiconductor ecosystem through successful project outcomes. **What You'll Need:** - Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field. - 2+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm). - Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimization, STA, EMIR, and physical verification. - Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime. - Strong scripting and automation skills using Python, PERL, TCL, or similar languages. - Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs. - Exposure to high-frequency design and low-power design methodologies. **Benefits:** - Comprehensive medical and healthcare plans that work for you and your family. - In addition to company holidays, we have ETO and FTO Programs. - Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. - Purchase Synopsys common stock at a 15% discount, with a 24-month look-back. - Save for your future with our retirement plans that vary by region and country. - Competitive salaries. ## Skills ### Required - RTL2GDSII flows - physical design - synthesis - place & route - clock tree synthesis (CTS) - timing optimization - static timing analysis (STA) - EMIR - physical verification - Python - PERL - TCL --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/soc-engineering-sr-engineer/44408/98213725744?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)