# Verification Engineer

**Company**: Cisco
**Location**: Pune
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Pune-India/ASIC-Engineering-Design-Verification-Leader_2013041?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_9353705f-487

## Description

Cisco's Client Optics Group (COG) designs and delivers high-speed optical transceivers and platforms that power Cisco's core data center networking solutions.

As a Verification Engineer, you will work with a diverse team of engineers spanning multiple disciplines to design, develop, and test advanced pluggable and Co-packaged Optics (CPO).

Your responsibilities include:

- Developing testbench components for Silicon Photonics subsystems using UVM methodology

- Creating verification documentation and working with senior engineers to define verification methodology

- Running verification at block and chip level with various high-speed IPs integrated

- Developing functional coverage models, assertions, and debugging complex verification issues

- Working with CPU FW loaded and verifying functionality at the CPU sub-system level

- Involvement in FPGA verification, ATE test plan and test vector generation, ATE testing, and release to production

Requirements:

- Bachelor's or Master's in Electronics Engineering (or equivalent/related)

- 8-12 years of functional verification experience

- Strong skills in SystemVerilog, Python, C, and UVM methodology

- Familiarity with UVM phases, configuration mechanisms, factory overrides, and reuse across block, subsystem, and SoC-level verification

- Good understanding of CPU sub-systems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & Protocols

- Experience with RTL design, simulation tools, and ASIC design flow

- Excellent organizational, teamwork, and communication skills

## Skills

### Required
- SystemVerilog
- Python
- C
- UVM methodology
- RTL design
- ASIC design flow
- FPGA
- ODSP
- SerDes
- Ethernet
- D2D PHY IP

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Pune-India/ASIC-Engineering-Design-Verification-Leader_2013041?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)