# Senior ASIC Design Engineer – Clocks IP

**Company**: NVIDIA
**Location**: Santa Clara
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---Clocks-IP_JR2003480?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_9260ec87-cb9

## Description

We are looking for a top-notch ASIC engineer to join the clocks group. The team is responsible for crafting all aspects of GPU and CPU clocking. As a Clocks team member, you will be architecting the clock domain to satisfy functional, physical and testing design requirements.

Engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural/design/physical constraints.

Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.

Collaborate with Physical design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking.

Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams.

Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.

BS in Electrical Engineering or equivalent experience (MS preferred)

3+ years of relevant work experience.

Deep understanding of logic optimization techniques and PPA trade-offs.

Excellent interpersonal skills and ability to collaborate with multiple teams.

Experience in RTL design (Verilog), verification and logic synthesis.

Strong coding skills in python or other industry-standard scripting languages.

Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.

Implementing on-chip clocking networks is a bonus

## Skills

### Required
- RTL design
- Verification
- Logic synthesis
- Python
- Sub-micron silicon issues

### Nice to have
- Clocks controller
- Clocks logic design
- System level artifacts
- Scalable designs
- Architecture

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---Clocks-IP_JR2003480?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)