Physical Design Engineer (Senior/Staff) in District 7
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. You have spent years in physical design where routing decisions determine whether a chip tapes out clean or burns weeks in ECO. You know Fusion Compiler or ICC2 from debugging congestion hotspots and timing violations at 2am, not from training slides. P&R is equal parts science and pattern recognition, and you have developed both. You do not wait for a perfect floorplan. You flag what will break and propose something workable before it becomes a schedule problem. When extraction results look wrong, you dig until you understand why. The best solutions often come from walking to the frontend team and asking the right question. Mentorship matters to you. You remember staring at a million DRC violations as a junior engineer, so you take time to show someone how to read a timing report or why their power grid will not close. You script your way out of repetitive work in TCL or PERL, and you know when automation helps versus when manual is faster. At Synopsys, you will work on real SOC designs using the tools the industry depends on. The problems are hard, the work is real, and what you build will matter. What You'll Be Doing Own physical implementation using Fusion Compiler or ICC2, from floorplanning through routing and signoff closure Debug complex P&R issues including timing, congestion, IR drop, and physical verification failures across hierarchical designs Guide customer design and CAD teams on tool usage, methodology, and design closure as a trusted technical advisor Develop physical design flows and automation scripts in TCL, PERL, or Python to improve efficiency Work with Synopsys BU and Sales teams to deploy tool and IP solutions that solve real customer problems Mentor junior engineers on P&R fundamentals, debugging techniques, and tool best practices The Impact You Will Have Accelerate customer tapeout schedules by solving physical design bottlenecks that would otherwise cause weeks of delay Improve Synopsys physical design methodologies through real-world deployment and customer feedback Enable successful Fusion Compiler and ICC2 adoption across customer teams, directly influencing tool ROI Reduce design respins by catching physical implementation problems early in the flow Build long-term team capability by elevating junior engineer skills and reducing external support dependency Shape EDA tool development by surfacing customer pain points that matter Contribute to silicon products powering AI, automotive, mobile, and data center applications worldwide What You'll Need Bachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or equivalent 3 to 6+ years hands-on Place and Route experience using Fusion Compiler or ICC2 on complex SOC or ASIC designs Strong knowledge of P&R, extraction, static timing analysis, IR drop, and physical verification fundamentals Proficiency in TCL, PERL, or Python scripting for automation and flow development Solid debugging skills to trace root causes across timing, power, signal integrity, and DRC/LVS domains Experience with signoff tools like PrimeTime, Redhawk, StarRC, or ICV is a plus Effective English communication skills for customer-facing and cross-functional work