# ASIC Design Verification Engineer

**Company**: Cisco
**Experience**: senior
**Job type**: full-time
**Salary**: $155,000.00 to $222,600.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Design-Verification-Engineer_2006886?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_8d2ab475-2dc

## Description

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.

As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You’ll architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips.

Your responsibilities include:

- Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure.

- Build DV environments from scratch for block and cluster levels.

- Develop, implement, and enhance test plans and tests for block and cluster verification, using both constraint-random and directed stimulus.

- Ensure comprehensive verification coverage through code and functional coverage implementation and review.

- Qualify RTL design by running Gate Level Simulations on netlists.

- Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration.

- Support design testing in emulation environments.

The minimum qualifications for this role are:

- Bachelors degree + 5 years of ASIC experience, or Masters degree+ 3 years of ASIC experience, or PhD + 0 years of related experience.

- Experience in System Verilog and UVM methodology.

- Hands-on experience building reusable and scalable test benches from scratch.

- Experience with scripting using Perl and/or Python.

Preferred qualifications include:

- Experience with forwarding logic, parsers, or P4.

- Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS.

- Knowledge of formal verification tools (e.g., IEV or VC Formal).

- Domain knowledge in one or more protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.

The starting salary range for this position is $155,000.00 to $222,600.00, and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

## Skills

### Required
- System Verilog
- UVM methodology
- Perl
- Python

### Nice to have
- forwarding logic
- parsers
- P4
- emulation platforms
- formal verification tools
- PCIe
- CXL
- Ethernet
- RDMA
- DDR
- TCP

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Design-Verification-Engineer_2006886?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)