# Sr Staff High-Speed Interface Verification Engineer

**Company**: Synopsys
**Location**: Hyderabad, Telangana
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/hyderabad/sr-staff-high-speed-interface-verification-engineer/44408/101997038208?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_8c2dbb58-15b

## Description

You are a seasoned verification engineer with expertise in mixed-signal environments, particularly in high-speed interface verification. You will lead the verification of high-speed SerDes IP using UVM and SystemVerilog testbenches in mixed-signal co-simulation environments. Your responsibilities include defining, tracking, and executing verification test plans for PCIE, Ethernet, USB3.1, and other high-speed protocols. You will also debug simulation failures, build and extend UVM testbenches, and collaborate with digital, analog, and mixed-signal design teams.

Your impact will be significant, ensuring that SerDes IP meets performance, functionality, and reliability targets before it reaches silicon. You will reduce post-silicon debug cycles, set the technical direction for verification methodology, and accelerate customer adoption and satisfaction.

To succeed in this role, you need:

- MTech or BTech in Electronics, Electrical Engineering, Computer Science, or equivalent with 7+ years of hands-on verification experience in ASIC or mixed-signal environments

- Deep expertise in UVM, SystemVerilog, and verification methodologies

- Proven experience with digital/analog co-simulation tools and methodologies

- Working knowledge of high-speed interface protocols such as PCIE, Ethernet, or USB3.1

- Strong understanding of the full ASIC development flow

- Experience writing complex system-level testbenches in UVM

- Hands-on experience debugging waveform-level failures

We offer a comprehensive range of health, wellness, and financial benefits, including competitive salaries, comprehensive medical and healthcare plans, time away, family support, ESPP, retirement plans, and more.

## Skills

### Required
- UVM
- SystemVerilog
- mixed-signal verification
- high-speed interface protocols
- ASIC development flow

---

Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/hyderabad/sr-staff-high-speed-interface-verification-engineer/44408/101997038208?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)