# Research Engineer, Chip Design RL (Reinforcement Learning)

**Company**: Anthropic
**Location**: San Francisco, CA
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: $500,000-$850,000 USD
**Category**: Engineering
**Industry**: Technology
**Wikidata**: https://www.wikidata.org/wiki/Q116758847

**Apply**: https://job-boards.greenhouse.io/anthropic/jobs/5231612008?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_8aa1ccab-5e0

## Description

Anthropic's mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole.

We're hiring for the Code RL team within the RL organization. As a Research Engineer, you'll advance our models' ability to design silicon. Hardware design is difficult and unforgiving – exactly the sort of domain we want Claude to excel at.

You'll leverage your chip design expertise and turn it into tasks and signals for models to learn from. Specifically, you will:

- Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal) verification, physical design optimization.

- Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.

- Conduct experiments and shape our roadmap.

- Deliver your work into research and production training runs.

- Collaborate with other researchers and engineers across and outside Anthropic.

You may be a good fit if you:

- Have expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place-and-route, timing closure), PPA optimization, DFT, ECOs.

- Are fluent with industry EDA tools and processes.

- Have taped out chips and have experience going from spec to silicon.

- Know how to balance research exploration with engineering implementation.

- Are passionate about AI's potential and committed to developing safe and beneficial systems.

Strong candidates may also have:

- Experience with reinforcement learning, evaluations or environments.

- Built tooling or automation around chip design flows.

- Worked on ML accelerators or high-performance compute hardware.

- Familiarity with high-level synthesis or architecture simulators.

The annual compensation range for this role is $500,000-$850,000 USD.

Logistics:

- Minimum education: Bachelor’s degree or an equivalent combination of education, training, and/or experience

- Required field of study: A field relevant to the role as demonstrated through coursework, training, or professional experience

- Minimum years of experience: Years of experience required will correlate with the internal job level requirements for the position

- Location-based hybrid policy: Currently, we expect all staff to be in one of our offices at least 25% of the time. However, some roles may require more time in our offices.

- Visa sponsorship: We do sponsor visas!

## Skills

### Required
- ASIC or FPGA design
- RTL
- design verification
- physical design
- EDA tools
- chip design

### Nice to have
- reinforcement learning
- evaluations or environments
- tooling or automation around chip design flows
- ML accelerators
- high-performance compute hardware
- high-level synthesis
- architecture simulators

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Source: [Apply at job-boards.greenhouse.io](https://job-boards.greenhouse.io/anthropic/jobs/5231612008?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)