# SoC Verification Engineer

**Company**: Synopsys
**Location**: Ho Chi Minh City
**Work arrangement**: onsite
**Experience**: entry
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/ho-chi-minh-city/soc-verification-engineer/44408/101938929984?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_898cd4ab-249

## Description

We are seeking a SoC Verification Engineer to join our team at Synopsys in Ho Chi Minh City, Vietnam. As a SoC Verification Engineer, you will be responsible for designing and developing cutting-edge semiconductor solutions. You will work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

**Job Description**

You have spent years in verification knowing that finding the bug before tapeout is the difference between a product that ships and one that doesn't. You understand that a good testbench is not about coverage numbers on a dashboard, it is about building an environment that stresses the design in ways that matter. You think in corner cases. When someone describes a new protocol feature, you are already mentally mapping the sequences that will break it.

**Responsibilities**

- Define block and subsystem verification plans that map directly to design specifications and protocol requirements

- Build UVM testbenches in System Verilog, including agents, scoreboards, coverage models, and assertion monitors

- Write constrained random and directed tests that exercise protocol compliance, corner cases, and error injection scenarios

- Debug RTL and testbench failures using simulators and waveform analysis to root cause and resolve issues

- Collaborate with RTL designers and global verification engineers to align on design intent and coverage goals

- Apply formal verification techniques to prove properties and close coverage gaps

- Drive verification closure by tracking coverage metrics and iterating on test plans until signoff

**Requirements**

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science or related fields

- 0-4 years of hands-on design verification experience in the semiconductor industry

- Proficiency in System Verilog and UVM for building testbenches and implementing coverage

- Knowledge of at least one protocol such as AMBA, PCI Express, CXL, UCIe, Ethernet, HBM, or DDR

- Experience with industry standard simulators like VCS, Xcelium, or Questa, and version control systems

- Solid scripting skills in Python, Perl, or Tcl for automation and regression management

**Benefits**

- Comprehensive medical and healthcare plans that work for you and your family

- In addition to company holidays, we have ETO and FTO Programs

- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more

- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back

- Save for your future with our retirement plans that vary by region and country

- Competitive salaries

## Skills

### Required
- System Verilog
- UVM
- protocol compliance
- corner cases
- error injection scenarios
- debug RTL and testbench failures
- formal verification techniques
- coverage metrics

### Nice to have
- Python
- Perl
- Tcl
- VCS
- Xcelium
- Questa

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/ho-chi-minh-city/soc-verification-engineer/44408/101938929984?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)