# ASIC Verification Engineer

**Company**: Hewlett Packard Enterprise
**Location**: Sunnyvale, CA
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: Annual Salary USD 124,000 - 251,000
**Category**: Engineering
**Industry**: Technology

**Apply**: https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Sunnyvale-California-United-States-of-America/ASIC-Design-Engineer-lll_1201839-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_88a49cba-440

## Description

We are seeking a highly motivated ASIC Verification Engineer to join our networking silicon development team. As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist.

**Key Responsibilities:**

- Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.

- Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.

- Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.

- Analyze simulation results using industry-leading simulation tools and debug waveforms to validate design functionality.

- Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.

**Required Skills and Qualifications:**

- 7+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.

- Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.

- Deep understanding of randomization, constraints, functional coverage, and assertions.

- Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.

- Proficiency with industry-standard simulation tools and waveform debugging.

**Preferred Skills and Experience:**

- Experience verifying networking ASICs or router datapath/control blocks.

- Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.

- Exposure to emulation environments, hardware acceleration, or traffic-model integration.

- Knowledge of coverage analytics, regression dashboards, and continuous-integration flows.

- Understanding of low-power or formal verification methodologies.

- Experience with post-silicon bring-up and debug.

**What We Can Offer You:**

- Comprehensive suite of benefits that supports physical, financial, and emotional wellbeing.

- Investment in your career through specific programs catered to helping you reach your career goals.

- Unconditional inclusion in the way we work and celebrate individual uniqueness.

## Skills

### Required
- SystemVerilog
- UVM
- ASIC verification
- SoC design
- simulation tools

### Nice to have
- networking ASICs
- high-speed interconnects
- emulation environments
- coverage analytics
- low-power verification

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