# RTL Design, Staff Engineer

**Company**: Synopsys
**Location**: Ho Chi Minh City
**Work arrangement**: onsite
**Experience**: staff
**Job type**: Employee
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/ho-chi-minh-city/rtl-design-staff-engineer-in-hcmc-da-nang-hanoi/44408/92454718864
**Canonical**: https://yubhub.co/jobs/job_85ea872e-b5f

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.

They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

**Job Description**

We are seeking an experienced RTL design engineer with a strong background in electronics or telecommunications.

With over five years in ASIC or PHY IP development, you’re passionate about solving technical challenges, collaborating with cross-functional teams, and mentoring others.

Your communication skills and attention to detail ensure projects run smoothly from specification to silicon debug.

You thrive in fast-paced environments and are eager to contribute to groundbreaking technology.

**Responsibilities**

- Develop RTL specifications and architectures for High Bandwidth Interface PHY IP.

- Define synthesis constraints and resolve STA and gate-level simulation issues.

- Collaborate with verification, controller, and lab teams for design and debugging.

- Support RTL to GDS flow during logic implementation.

- Lead projects and train junior engineers.

- Work with customers to resolve technical RTL issues.

**The Impact You Will Have**

- Deliver robust RTL designs for advanced silicon solutions.

- Drive successful project completion and tape-outs.

- Enhance design quality and verification efficiency.

- Support customer success and strengthen Synopsys’ reputation.

- Mentor and grow engineering talent within the team.

- Contribute to digital flow improvements and innovation.

**What You’ll Need**

- BS/MS/PhD in Electronics Engineering or Telecommunications.

- 5+ years of RTL design experience for ASIC or PHY IP.

- Expertise in VCS, Verdi, Spyglass, and scripting (Perl, TCL, Python).

- Knowledge of clock domain crossing, APB, JTAG protocols.

- Strong English communication skills.

**Who You Are**

- Responsible, result-oriented, and self-motivated.

- Collaborative and proactive problem solver.

- Effective communicator and mentor.

**The Team You’ll Be A Part Of**

Join a collaborative engineering team delivering innovative PHY IP solutions.

Work alongside experts in Ho Chi Minh City, Da Nang, or Hanoi, and contribute to Synopsys’ global leadership in semiconductor technology.

**Rewards and Benefits**

We offer a comprehensive range of health, wellness, and financial benefits.

Your recruiter will provide more details about salary and benefits during the hiring process.

## Skills

### Required
- RTL design
- ASIC or PHY IP development
- VCS
- Verdi
- Spyglass
- Perl
- TCL
- Python
- Clock domain crossing
- APB
- JTAG protocols