# Senior ASIC Design Engineer

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer_JR2017358?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_8358d8a0-e3b

## Description

NVIDIA is seeking a Senior ASIC Design Engineer for its Circuit Solutions Group. The engineer will work on micro-architecture and digital design implementation of innovative IPs for hardware security, clocking, voltage regulation, and silicon correlation.

Responsibilities:

- Lead the micro-architecture and digital design implementation of various IPs

- Collaborate with architects, circuit designers, and verification engineers

- Develop scalable RTL designs and execute synthesis and timing analysis

- Perform functional verification, CDC checks, and formal equivalence

- Support post-silicon bring-up and debug activities

- Develop tools and flows, including Agentic AI flows

Requirements:

- BS in Electrical Engineering, Computer Engineering, or related field; MS or PhD a plus

- 3+ years of experience in logic design, Verilog, and/or System-Verilog

- Understanding of physical design and VLSI

- Experience with multiple clock domains and asynchronous interfaces

- Exposure to digital systems design and computer architecture

- Programming skills in PERL or Python

- Excellent communication and interpersonal skills

Preferred qualifications:

- Experience with all stages of ASIC design flow

- Understanding of behavioral real number modeling and low-level digital or mixed-signal design concepts

- Knowledge of mixed-signal and custom-designed IPs solutions

- Proficiency in scripting languages like Perl, Tcl, and Makefiles

NVIDIA offers competitive salaries and a comprehensive benefits package.

## Skills

### Required
- ASIC design
- Digital design
- Verilog
- System-Verilog
- VLSI
- PERL
- Python
- RTL design
- Synthesis
- Timing analysis

### Nice to have
- Mixed-signal design
- Custom-designed IPs
- Tcl
- Makefiles
- Agentic AI flows

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer_JR2017358?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)