# ASIC Verification- Senior Staff Engineer

**Company**: Synopsys
**Location**: Bengaluru, Karnataka
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/bengaluru/asic-verification-senior-staff-engineer/44408/100721402128?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_826ee951-653

## Description

You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications.

**Responsibilities:**

- Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.

- Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.

- Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.

- Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics.

- Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure.

- Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity.

- Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.

**Requirements:**

- BSEE with 8 years or MSEE with 6+ years of relevant experience in ASIC or IP verification.

- Expertise in developing HVL (System Verilog)-based verification environments and testbenches.

- Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.

- Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable.

- Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.

- Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus.

- Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.

**Benefits:**

- Comprehensive medical and healthcare plans that work for you and your family.

- In addition to company holidays, we have ETO and FTO Programs.

- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.

- Save for your future with our retirement plans that vary by region and country.

- Competitive salaries.

## Skills

### Required
- System Verilog
- UVM
- OVM
- VMM
- Perl
- TCL
- Python
- MIPI-I3C
- UFS
- AMBA
- Ethernet
- DDR
- PCIe
- USB

### Nice to have
- formal verification
- VIP development

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/asic-verification-senior-staff-engineer/44408/100721402128?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)