# DFT Architect

**Company**: Cisco
**Location**: San Jose
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: $167,700.00 to $245,200.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/Senior-ASIC-DFT-DV-Engineer--Hybrid-_2027869?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_804a4bf3-729

## Description

Join the Silicon One team at Cisco as a DFT Architect. This hybrid role requires three days per week at Cisco's San Jose location.

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally.

As a DFT Architect, you will be responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug, and diagnostics needs of the design.

Key responsibilities:

- Own the MBIST methodology across the Silicon One portfolio, driving unified, high-quality standards for memory testing.

- Architect reusable, hierarchical infrastructures that scale across massive designs to accelerate time-to-market for future silicon.

- Work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification.

Requirements:

- Bachelor's in Electrical Engineering or equivalent with at least 7+ years (or Master's with 4+ years) of experience.

- Prior experience in test planning based on complex design specification.

- Experience debugging using DVE/Verdi.

- Prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes.

- Experience with TCL, Python, or Perl.

Preferred qualifications:

- Experience in Verilog/SV.

- Experience addressing memory failure correlation in production.

- Experience in silicon testing and Automatic Test Equipment (ATE).

- Experience with industry-standard DFT tools (e.g., Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent).

Benefits:

- Medical, dental, and vision insurance.

- 401(k) plan with a Cisco matching contribution.

- Paid parental leave.

- Short and long-term disability coverage.

- Basic life insurance.

- Paid time away (vacation, holidays, sick time).

- Optional 10 paid days per full calendar year to volunteer.

Salary range: $167,700.00 to $245,200.00 per year.

## Skills

### Required
- Electrical Engineering
- Test Planning
- DFT Architecture
- Memory Architectures
- TCL
- Python
- Perl
- DVE/Verdi

### Nice to have
- Verilog/SV
- Memory Failure Correlation
- Silicon Testing
- Automatic Test Equipment (ATE)
- Synopsys DesignWare
- SMS
- TestMax
- Mentor Graphics Tessent

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/Senior-ASIC-DFT-DV-Engineer--Hybrid-_2027869?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)