# Applications Engineering, Sr. Staff Engineer **Company**: Synopsys **Location**: Sunnyvale, California **Experience**: senior **Job type**: full-time **Salary**: $157000-$235000 **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/sunnyvale/applications-engineering-sr-staff-engineer/44408/100768196016?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_7fda9b16-a9e ## Description We are seeking an experienced Sr. Staff Engineer to join our Applications Engineering team at Synopsys. As a technical expert, you will work directly with customers to demonstrate and implement Synopsys physical design tools, debug complex design issues, and develop technical methodologies. You have spent years in the trenches of physical design, not just running tools but understanding why a clock tree converges or falls apart, why congestion shows up in one corner and not another, and what it actually takes to close timing at 3nm when the margin for error is measured in picoseconds. **Responsibilities** - Support pre-sales and post-sales engagements with semiconductor customers, demonstrating Synopsys physical design tools including Fusion Compiler and ICC2 in live technical sessions - Debug complex physical design issues across the RTL-to-GDSII flow, working directly with customer design teams to resolve placement, routing, timing closure, and congestion challenges at advanced nodes - Develop and deliver technical methodologies for clock tree synthesis, AI-driven optimization, macro placement, and timing closure that customers can adopt in production flows - Build proof-of-concept designs and benchmarks that show measurable PPA improvements using Synopsys tools compared to customer baseline flows - Collaborate with product engineering teams to translate customer pain points into feature requests, tool enhancements, and methodology improvements - Train customer engineers on advanced Synopsys tool capabilities, from multi-scenario optimization to noise-aware routing techniques - Travel to customer sites to provide hands-on technical support during critical project phases, including tape-out preparation and bring-up **The Impact You Will Have** - Accelerate customer adoption of Synopsys tools, directly contributing to revenue growth and competitive wins in key accounts - Help customers achieve measurable improvements in PPA (power, performance, area) and reduce their time to tape-out by weeks or months through better methodologies - Influence the product roadmap by surfacing real-world customer challenges that shape the next generation of Fusion Compiler and ICC2 capabilities - Build long-term technical relationships with leading semiconductor companies, becoming the trusted expert they call when a design is stuck - Enable customers to successfully adopt advanced node technologies (5nm, 3nm, and beyond) where traditional methodologies break down - Expand Synopsys footprint within accounts by demonstrating value across multiple design teams and product lines - Contribute to the technical reputation of Synopsys in the industry through customer success stories, white papers, and conference presentations **Requirements** - Bachelor's degree in Electrical Engineering or equivalent with 9+ years of hands-on ASIC physical design experience, or Master's degree with 7+ years - Deep expertise in RTL-to-GDSII flows using industry-standard tools, with direct experience in placement, optimization, clock tree synthesis, and routing - Hands-on proficiency with Synopsys backend tools including Fusion Compiler, ICC2, Design Compiler, and PrimeTime - Strong understanding of advanced node design challenges (7nm and below), including FinFET effects, multi-patterning constraints, and electromigration - Experience with timing closure techniques, multi-scenario optimization, and noise analysis in complex SoC designs - Knowledge of clock tree synthesis methodologies including H-Tree and multi-source CTS is a strong plus - Willingness to travel up to 30% to customer sites for technical engagements and on-site support ## Skills ### Required - ASIC physical design - RTL-to-GDSII flows - Synopsys backend tools - Fusion Compiler - ICC2 - Design Compiler - PrimeTime - clock tree synthesis - timing closure techniques - multi-scenario optimization - noise analysis ### Nice to have - H-Tree - multi-source CTS --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/sunnyvale/applications-engineering-sr-staff-engineer/44408/100768196016?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)