# LPDDR IP Design Senior Staff Engineer

**Company**: Synopsys
**Location**: Bengaluru, Karnataka
**Experience**: senior
**Job type**: employee
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/bengaluru/lpddr-ip-design-senior-staff-engineer/44408/93763201616?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_7f97c1cb-2e7

## Description

We are looking for a Sr. Staff ASIC Digital Design Engineer to join Synopsys LPDDR PHY IP team to innovate and develop the latest world-class market-leading DesignWare LPDDR PHY IP solution.

In this role, you will be in a leadership role to contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs.

Responsibilities:

- Designing and micro-architecting LPDDR PHY IP writing Verilog and SystemVerilog code and design specification

- Conduct simulation and analysis of designs working with Verification, Timing, DFT, and Power team members

- Analyzing and fixing Lint, CDC/RDC, DFT, Timing, and power issues

- Maintain and improve design automating flow and process

Requirements:

- BS in Electrical Engineering and a minimum of 6 years of experience in complex technical development

- Experience with synthesizable Verilog and System Verilog design concepts, coding, and implementation

- Experience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques

- Exhibit excellent communication skills and be self-motivated

- Understanding of memory and memory PHY architecture is a plus

Benefits:

- Comprehensive medical and healthcare plans that work for you and your family

- In addition to company holidays, we have ETO and FTO Programs

- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more

- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back

- Save for your future with our retirement plans that vary by region and country

- Competitive salaries

## Skills

### Required
- Verilog
- SystemVerilog
- ASIC design
- DFT
- Timing analysis
- Power optimization

### Nice to have
- memory PHY architecture

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/bengaluru/lpddr-ip-design-senior-staff-engineer/44408/93763201616?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)