# Senior Staff Technical Applications Engineer, STA & ECO

**Company**: Synopsys
**Location**: Raanana, Central District
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/raanana/senior-staff-technical-applications-engineer-sta-and-eco/44408/101040901216?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_7cd362f4-47b

## Description

You will engineer the future with Synopsys, a leader in engineering solutions from silicon to systems.

As a Senior Staff Technical Applications Engineer, STA & ECO, you will drive adoption of PrimeTime and PrimeClosure across customer accounts, working directly with design teams to integrate the tools into their flows.

Your main responsibilities will include:

- Driving adoption of PrimeTime and PrimeClosure across customer accounts in both pre-sale evaluations and post-sale deployment

- Running competitive benchmarks against other STA tools, documenting performance, accuracy, and capacity advantages in real customer design contexts

- Delivering hands-on training sessions and technical workshops to customer engineering teams, covering timing closure methodology, ECO flows, and advanced PrimeTime features

- Partnering with R&D and product marketing to translate customer pain points into feature requests, providing detailed use cases and technical requirements that shape the product roadmap

- Troubleshooting complex timing issues in customer designs, diagnosing problems related to timing corners, process variation, crosstalk, and signal integrity

- Presenting technical solutions and methodology recommendations to both design engineers and engineering management, tailoring the message to each audience

- Building and maintaining technical relationships with key customers, becoming their trusted advisor for timing closure challenges

The impact you will have includes:

- Enabling successful tapeouts at advanced nodes by helping customers close timing on schedules that directly affect their product launch dates

- Increasing PrimeTime and PrimeClosure adoption across your customer base, growing tool usage and expanding Synopsys's footprint in critical accounts

- Reducing customer time spent fighting timing issues by delivering methodology improvements and best practices that make their flows more efficient

- Feeding high-quality customer feedback into R&D, directly influencing which features get prioritized and how they get implemented

- Strengthening Synopsys's competitive position by winning benchmarks and proving tool superiority in head-to-head evaluations

- Building long-term technical partnerships with customers that lead to renewals, expansions, and references for new business

- Elevating the expertise of customer teams through training and knowledge transfer, creating advocates who champion Synopsys tools internally

To be successful in this role, you will need:

- Solid working knowledge of Static Timing Analysis and ECO closure, with the ability to explain timing concepts, constraints, and methodologies to design teams

- Direct experience with at least two chip tapeouts at 16nm or below nodes, where you were responsible for timing closure or ECO implementation

- Hands-on proficiency with Synopsys PrimeTime, including experience running STA, analyzing timing reports, and debugging violations

- Understanding of timing corners, process variation (OCV, AOCV, POCV), and signal integrity effects like crosstalk and IR drop

- Experience with ECO flows using PTECO or PrimeClosure, including gate sizing, buffer insertion, and logic restructuring

- BSEE or equivalent with 5+ years of relevant experience, or MSEE with 3+ years, focused on digital design, timing analysis, or applications engineering

- Familiarity with scripting in TCL or Python to automate analysis tasks and customize flows is a plus

## Skills

### Required
- Static Timing Analysis
- ECO closure
- PrimeTime
- chip tapeouts
- timing closure
- ECO implementation
- STA
- timing analysis
- digital design

### Nice to have
- TCL
- Python

---

Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/raanana/senior-staff-technical-applications-engineer-sta-and-eco/44408/101040901216?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)