# Senior ASIC Design Engineer – Clocks IP

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---Clocks-IP_JR2022532?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_7a6f34a9-f3f

## Description

The Clocks team at NVIDIA is seeking a senior ASIC Design Engineer to join their team, focusing on crafting all aspects of GPU and CPU clocking. As a Clocks team member, you will architect the clock domain to satisfy functional, physical, and testing design requirements.

You will engage with multiple teams to design GPU or CPU clocks that meet architectural, design, and physical constraints, while improving Power, Performance, and Area (PPA) of innovative NVIDIA chips.

Key responsibilities include:

- Designing GPU or CPU clocks with multiple teams to satisfy architectural, design, and physical constraints

- Improving PPA of NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization, and Ease of timing closure

- Collaborating with Physical design and timing teams to evaluate Clocking concerns and develop solutions

- Delivering clock RTL information to GPU, CPU, and SOC verification teams, timing and DFT teams

- Participating in the end-to-end cycle of ASIC execution from micro-arch to Silicon bringup

Requirements:

- BS in Electrical Engineering or equivalent experience (MS preferred)

- 3+ years of relevant work experience

- Deep understanding of logic optimization techniques and PPA trade-offs

- Excellent interpersonal skills and ability to collaborate with multiple teams

- Experience in RTL design (Verilog), verification, and logic synthesis

- Strong coding skills in Python or other industry-standard scripting languages

- Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus

Preferred qualifications:

- Experience with clocks controller, clocks logic design

- Understanding of system-level artifacts like power, noise, etc.

- Experience with scalable designs and architecture

- Hands-on silicon debug experience

NVIDIA offers competitive salaries and a generous benefits package.

## Skills

### Required
- ASIC design
- RTL design
- Verilog
- logic synthesis
- Python
- DFx
- Physical Implementation
- Power Optimization

### Nice to have
- clocks controller
- clocks logic design
- scalable designs
- silicon debug

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-ASIC-Design-Engineer---Clocks-IP_JR2022532?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)