# Senior System Architecture Specialist **Company**: Synopsys **Location**: Moreira, Porto **Experience**: senior **Job type**: full-time **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/moreira/senior-system-architecture-specialist/44408/98706276736?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_7a2e9e69-86a ## Description You are a UCIe / Die-to-Die System Architecture Specialist who can work directly with customer architects to close real system-level chiplet and multi-die design decisions. You will help customers integrate die-to-die IPs into complex ASIC, SoC, and multi-die platforms, identify key requirements or gaps, and translate customer feedback into actionable input for Synopsys Product Management, R&D, and roadmap planning. Responsibilities: - Own the technical architecture engagement for UCIe / die-to-die IP with strategic customers, from early chiplet and multi-die platform requirements through architecture closure and initial deployment readiness. - Work with customer architects and engineering teams to define suitable UCIe/ die-to-die subsystem configurations for advanced ASIC, SoC, and multi-die platforms. - Analyze system-level trade-offs related to protocol selection, bandwidth, latency, power, area, packaging considerations, validation, compliance, and interoperability. - Translate customer platform requirements, integration constraints, and deployment feedback into clear input for Synopsys Product Management, R&D, and roadmap planning. - Support technical closure of design wins by providing architecture guidance, configuration recommendations, risk assessment, and competitive positioning. - Develop reusable technical material, application notes, and customer-facing guidance based on real engagement experience. - Train FAEs and customer teams on UCIe architecture, die-to-die integration trade-offs, validation expectations, and deployment best practices. The Impact You Will Have: - Improve the quality of UCIe / die-to-die design wins by ensuring customer chiplet and multi-die architectures are technically sound before commitment. - Strengthen the Synopsys UCIe roadmap by feeding real customer system, packaging, protocol, and integration requirements into product planning and R&D execution. - Reduce customer integration risk by identifying architecture, configuration, validation, interoperability, and implementation issues early. - Help establish Synopsys as a trusted technical partner for next-generation AI, HPC, automotive, networking, and chiplet-based platforms. - Provide technical training to FAEs and key customers on UCIe architecture, die-to-die IP products, integration trade-offs, and deployment best practices. Requirements: - Bachelor’s and/or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or Computer Science. - 5+ years of experience in semiconductor IP, SoC architecture, systems engineering, applications engineering, silicon validation, or customer-facing technical roles. - Solid understanding of UCIe / die-to-die IP concepts and system integration considerations. - Good system-level understanding of ASIC, SoC, and multi-die integration, with the ability to evaluate key performance and implementation trade-offs. - Experience engaging directly with customer architects, design teams, validation teams, and technical decision-makers. - Ability to translate ambiguous customer requirements into clear technical recommendations, product feedback, and closure plans. - Strong technical communication skills, including clear written analysis, structured trade-off explanation, and ability to align customer, sales, product, and engineering teams. Nice to Have: - Familiarity with one or more protocols commonly used in chiplet and die-to-die systems, such as AXI, PCIe, CXL, CHI-C2C, CXS, or Streaming. - Familiarity with multi-die architectures, advanced packaging technologies, and associated integration trade-offs. - Prior experience selecting, using, designing, or supporting internal or external IP. - Prior experience in application engineering or another direct customer-facing role. - Familiarity with implementation or validation flows, including RTL design, verification, synthesis, static timing analysis, simulation, or silicon bring-up. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. ## Skills ### Required - UCIe - die-to-die IP - ASIC - SoC - multi-die integration - system architecture - technical communication ### Nice to have - AXI - PCIe - CXL - CHI-C2C - CXS - Streaming - multi-die architectures - advanced packaging technologies --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/moreira/senior-system-architecture-specialist/44408/98706276736?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)