# Senior Silicon Product Development Engineer

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: senior
**Job type**: full-time
**Salary**: 168,000 USD – 258,750 USD for Level 4; and 200,000 USD – 322,000 USD for Level 5
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Silicon-Product-Development-Engineer_JR2023436?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_79b12818-6d6

## Description

NVIDIA is looking for a Senior Silicon Product Development Engineer to join the GPU PDE team. You will manage product bring-up from pre-silicon to launch, driving complex schedules and resolving problems through analytical techniques.

**Responsibilities:**

- Develop and implement ATE test content for the product line.

- Create and maintain project plans to meet market delivery timelines.

- Impact manufacturing yields, minimize excess, and contribute to business administration by predicting test durations and analyzing characterization outcomes.

- Manage key vendor relationships, particularly with Foundry, Assembly, and Memory vendors.

- Collaborate with Supply and Demand program management to meet chip quality levels.

**Requirements:**

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience.

- 7+ years of direct PDE experience.

- Strong problem-solving skills and a proven track record in ASIC Mixed Signal build, characterization, and qualification of BIST and SCAN DFT methodologies.

- Knowledge of advanced Silicon Process technology, such as FinFET.

- Hands-on experience in Chip-On-Wafer-On-Substrate Assembly, Silicon GPU Product Engineering, and HBM Memory vendor management.

- Excellent interpersonal skills for effective collaboration.

**Preferred Qualifications:**

- Comprehensive understanding of Memory testing methodology.

- In-depth knowledge of assembly stacking processes and vendor management.

- Strong grasp of all aspects of GPU characterization, wafer, and final test DFT coverage.

The base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 168,000 USD – 258,750 USD for Level 4; and 200,000 USD – 322,000 USD for Level 5. You will also be eligible for equity and benefits.

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## Skills

### Required
- Electrical Engineering
- Computer Engineering
- ASIC Mixed Signal build
- DFT methodologies
- FinFET
- Chip-On-Wafer-On-Substrate Assembly
- Silicon GPU Product Engineering
- HBM Memory vendor management

### Nice to have
- Memory testing methodology
- assembly stacking processes
- GPU characterization

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Silicon-Product-Development-Engineer_JR2023436?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)