# Physical Design Engineer

**Company**: Cisco
**Location**: San Jose, California
**Experience**: senior
**Job type**: full-time
**Salary**: $167,700.00 to $245,200.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Physical-Design-Engineer_2015743-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/job/physical-design-engineer-781a0e66-e01/

## Description

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms powering Cisco’s core Switching, Routing, and Wireless products.

As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes.

Responsibilities:

- Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 2nm).

- Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.

- Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.

- Implement and manage timing ECO strategies using tools like Prime Closure/PrimeTime.

- Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements.

- Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency.

- Evaluate and implement new timing methodologies; provide creative debugging solutions.

- Contribute to best practices and drive methodology alignment across projects.

Minimum Qualifications:

- Bachelors degree in Electrical Engineering + 5 years of related experience, or Masters degree in Electrical Engineering + 2 years of related experience, or PhD in Electrical Engineering 0+ years of related experience.

- Hands-on experience in ASIC physical design and implementation.

- Experience working with hierarchical floorplanning, clock and power distribution, global signal and I/O planning along with physical convergence, timing closure, and hierarchical design methodology.

- Prior experience with power integrity analysis and working on designs >100M gates in advanced nodes (16nm, 14nm, 7nm, 5nm, 3nm, 2nm).

Preferred Qualifications:

- Experience with Scripting using languages such as TCL, Python and efficient use of AI tools.

- Place & Route experience using tools such as Cadence Innovus or Synopsys FC.

- Synthesis experience including Cadence Genus/Synopsys FC.

- Formal Verification experience using tools such Synopsys Formality or Cadence LEC

- Experience with Static Timing Analysis including tools such as PrimeTime-DMSA.

- Experience with Power Integrity including tools such as Apache Redhawk/Voltus

- Physical Verification experience including tools such as Synopsys ICV or Mentor Calibre.

Benefits:

- Medical, dental and vision insurance

- 401(k) plan with a Cisco matching contribution

- Paid parental leave

- Short and long-term disability coverage

- Basic life insurance

- 10 paid holidays per full calendar year

- 1 paid day off for employee’s birthday

- Paid year-end holiday shutdown

- 4 paid days off for personal wellness

- 80 hours of sick time off provided on hire date and each January 1st thereafter

- Optional 10 paid days per full calendar year to volunteer

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## Skills

### Required
- ASIC physical design
- hierarchical floorplanning
- clock and power distribution
- static timing analysis
- Power Integrity Analysis

### Nice to have
- Scripting
- TCL
- Python
- AI tools
- Cadence Innovus
- Synopsys FC
- Power Integrity

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Physical-Design-Engineer_2015743-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)