# Senior DFT Power Methodology Engineer

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-DFT-Power-Methodology-Engineer_JR2021098-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_77fadfba-b41

## Description

As a Senior DFT Power Methodology Engineer at NVIDIA, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas.

Your responsibilities will include:

- Developing groundbreaking low power & thermal solutions for manufacturing tests

- Partnering with multi-functional teams to implement brand-new methodologies

- Working on post-silicon data analysis for power to architect next-gen solutions

- Helping develop and deploy DFT methodologies using Applied ML & Gen AI solutions

- Mentoring junior engineers on test designs and trade-offs

Requirements:

- BSEE (or equivalent experience) with 12+, MSEE with 10+, or PhD with 6+ years of experience in DFT design & power

- Understanding of fundamental DFT topics and VLSI areas of power, timing & voltage noise

- Experience in Power Analysis, Thermal Analysis & IR Drop tools is a plus

- Experience in application of AI for EDA-related problem-solving is a plus

- Excellent knowledge in using statistical tools for data analysis & insights

- Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power

- Experience in Silicon debug and bring-up on the ATE or SLT platforms

NVIDIA offers highly competitive salaries and a comprehensive benefits package, including equity and benefits.

## Skills

### Required
- DFT design
- power analysis
- thermal analysis
- IR Drop tools
- statistical tools
- VLSI
- RTL design
- STA
- place-n-route
- Silicon debug
- AI for EDA

### Nice to have
- Experience in managing DFT Power Methodology for designs
- post-silicon debug for thermal & IR Drop
- Outstanding written and oral communication skills

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-DFT-Power-Methodology-Engineer_JR2021098-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)