# Senior Physical Design Engineer

**Company**: NVIDIA
**Location**: Hsinchu
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Taiwan-Hsinchu/Senior-Physical-Design-Engineer_JR2017771?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_75f3f8a2-3b1

## Description

We are looking for a senior engineer to join our mixed-signal design team building next-generation NVLINK. This position offers the opportunity to have real impact in a dynamic technology-focused company. As a senior physical design engineer, you will be responsible for implementing complex high-performance and low-power SOCs. Your expertise will be invaluable in driving the success of our products, which range from consumer graphics to self-driving cars and artificial intelligence.

**Responsibilities:**

- Responsible for STA/design constraint for advanced technology nodes.

- Debugging timing violations and rolling in functional, timing ECOs and netlist formal verification.

- Responsible for floor planning and place and route (P&R) of high-performance chip partitions.

- Work on power grid planning, clock tree synthesis (CTS) and timing closure.

- Multi-mode and multi-corner timing closure, RC extraction, cross-talk, IR drop and EM analysis.

- Physical verification including ERC, DRC, LVS, etc.

**Requirements:**

- BSEE/MSEE or equivalent experience.

- Minimum 5+ years of experience in VLSI physical design implementation on 16nm, 7nm, 5nm or 3nm technology.

- Able to assist in design flow development and debugging.

- Strong analytical and debugging skills.

- Proficiency using Python, Perl, Tcl, Make scripting is desired.

## Skills

### Required
- RTL2GDS
- STA/design constraint
- timing violations
- functional, timing ECOs
- netlist formal verification
- floor planning
- place and route (P&R)
- power grid planning
- clock tree synthesis (CTS)
- timing closure
- multi-mode and multi-corner timing closure
- RC extraction
- cross-talk
- IR drop
- EM analysis
- physical verification
- ERC
- DRC
- LVS

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Taiwan-Hsinchu/Senior-Physical-Design-Engineer_JR2017771?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)