# Principal Digital Verification Engineer

**Company**: Synopsys
**Location**: Nepean, Ontario
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Salary**: $146000-$219000
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/nepean/principal-digital-verification-engineer/44408/100812692208?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_7295b450-03f

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years building verification environments for complex digital designs where mistakes show up as silicon respins or customer escalations. The difference between a PHY that passes regression and one that works in production is something you understand deeply, and it shapes how you write testplans, model coverage, and design infrastructure.

**Responsibilities**

- Develop comprehensive testplans and functional coverage models for training firmware running on RTL models of memory PHYs

- Build and maintain testbench infrastructure in SystemVerilog and UVM that supports complex verification scenarios across multiple product generations

- Create test cases that cover success paths, corner cases, and negative scenarios based on standard specifications and feature enhancements

- Debug complex issues across firmware, RTL, and testbench layers using simulation and waveform analysis tools

- Participate in technical reviews with architecture and implementation teams to influence design decisions from a verification perspective

- Research and evaluate emerging technologies in virtual prototyping and emulation to improve team efficiency, throughput, and quality

- Mentor junior engineers on testbench design, debugging techniques, and verification methodology while collaborating with other principal-level engineers on verification strategy

**The Impact You Will Have**

- Your testplans and coverage models will define the quality bar for memory interface IP that powers next-generation products across the industry

- The testbench infrastructure you build will accelerate verification cycles and enable the team to scale as new product lines come online

- Your debugging expertise will catch critical issues before they reach customers, protecting both product schedules and Synopsys reputation

- Technical reviews you contribute to will shape architecture decisions early, preventing costly verification bottlenecks downstream

- New verification technologies you evaluate and adopt will directly improve team productivity and reduce verification time

- Engineers you mentor will carry forward the verification rigor and problem-solving approach that makes complex IP actually work

- Your work with customers (on simulation debug or post-silicon bring-up debug) will strengthen their confidence in our IP and inform future product roadmaps

**Requirements**

- BSc in Electrical Engineering, Computer Engineering, or related field with 12+ years of verification experience, MSc with 10+ years, or PhD with 8+ years

- Deep proficiency in SystemVerilog and UVM, with a track record of building reusable testbench components and verification environments

- Strong command of simulation tools, waveform debuggers, and the ability to trace issues across multiple abstraction layers

- Solid understanding of C and experience with software/hardware co-simulation

- Experience with assertion-based verification, coverage analysis, and protocol-oriented performance debug

- Comfort working in Linux environments with scripting for regression systems, build automation, and source control workflows

- Experience with virtual prototyping or emulation platforms is a strong plus, as is knowledge of LPDDR5/5X and LPDDR6 or other memory interface standards

**Benefits**

- Comprehensive medical and healthcare plans that work for you and your family

- In addition to company holidays, we have ETO and FTO Programs

- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more

- Purchase Synopsys common stock at a 15% discount, with a 24-month look-back

- Save for your future with our retirement plans that vary by region and country

- Competitive salaries

## Skills

### Required
- SystemVerilog
- UVM
- simulation tools
- waveform debuggers
- C
- assertion-based verification
- coverage analysis
- protocol-oriented performance debug
- Linux
- scripting
- regression systems
- build automation
- source control workflows

### Nice to have
- virtual prototyping
- emulation platforms
- LPDDR5/5X
- LPDDR6

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/nepean/principal-digital-verification-engineer/44408/100812692208?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)