# Characterization Engineer

**Company**: Cisco
**Location**: Armenia
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/Armenia/Standard-Cells-Characterization-Engineer_2023258?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_71bee9ff-daf

## Description

The Common Hardware Group at Cisco is seeking a Characterization Engineer to lead the end-to-end characterization flow for standard cell libraries.

Responsibilities:

- Lead the end-to-end characterization flow for standard cell libraries from extracted netlists through Liberty delivery and correlation against TSMC reference data.

- Define and maintain PrimeLib/Liberate characterization methodology, templates, and automation for timing, power, noise, and leakage across PVT and RC corners.

- Drive correlation closure for delay, transition, capacitance, and leakage.

- Own extraction-to-char integration: LVS/StarRC setup, RC corner alignment, well-bias port handling, and netlist quality gates.

- Debug characterization failures at the netlist, simulation, and Liberty-model level.

- Develop reusable Tcl/shell flows, validation checks, and documentation for repeatable characterization.

- Partner with library design, physical verification, and CAD teams on cell readiness, deck configuration, and release criteria.

- Lead characterization reviews and define sign-off criteria.

Minimum Qualifications:

- Bachelor's degree in Electrical Engineering, Computer Science, or a related field and 6 years of relevant experience, or Master's Degree and 4 years of experience, or PhD and 1 year of experience.

- First-hand experience characterizing standard cell libraries with PrimeLib, Liberate, or equivalent tools.

- Strong understanding of Liberty formats and TSMC characterization flows.

- Experience with parasitic extraction, LVS, and RC corner/PVT alignment.

- Solid understanding of CMOS device behavior, timing arcs, power domains, and well/substrate bias effects.

Preferred Qualifications:

- Experience on advanced nodes with foundry std-cell libraries.

- Familiarity with TSMC N2P char packages, SPICE kits, and extraction guides.

- Experience with LVF/statistical characterization and hold-margin flows.

- Background in library QA, automated correlation reporting, and release management.

- Proficiency in Tcl, Perl, or Python for flow automation and correlation analysis.

## Skills

### Required
- PrimeLib
- Liberate
- TSMC
- Liberty formats
- parasitic extraction
- LVS
- CMOS device behavior

### Nice to have
- advanced nodes
- TSMC N2P
- LVF/statistical characterization
- library QA
- Tcl
- Perl
- Python

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