# ASIC Design Engineer - New College Grad 2026

**Company**: NVIDIA
**Location**: Santa Clara
**Work arrangement**: onsite
**Experience**: entry
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Design-Engineer---New-College-Grad-2026_JR2017581?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_718f9a93-f9f

## Description

Today, NVIDIA is tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world.

As an NVIDIAN, you'll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Come join the team and see how we can make a lasting impact on the world.

NVIDIA is looking for an ASIC Design Engineer - New College Grad 2026 to join our Memory Subsystem Team!

**Responsibilities:**

- Collaborate with architects/design verification/formal verification/physical design team to deliver a world-class solution. NVIDIA SOC Interconnects are among the industry's most sophisticated because of the complex area, latency, power, bandwidth and quality-of-service requirements.

- Be responsible for the micro-architecture and design including RTL design, synthesis and timing analysis using innovative CAD tools and using the latest process technologies.

**Requirements:**

- Currently pursuing or recently completed a BS or MS in Electrical Engineering or Computer Engineer or related degree (or equivalent experience).

- Exposure to high-speed coherent interconnects, protocol bridges, hardware-managed coherency and system level caches.

- Experience with multiple clock domains and asynchronous interfaces

- Knowledge of industry specifications like CHI/CXL/PCI-E is a plus.

- Strong proficiency of Verilog or VHDL.

- Scripting language like PERL

## Skills

### Required
- Verilog
- VHDL
- PERL
- CHI/CXL/PCI-E
- High-speed coherent interconnects
- Protocol bridges
- Hardware-managed coherency
- System level caches
- Multiple clock domains
- Asynchronous interfaces

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Design-Engineer---New-College-Grad-2026_JR2017581?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)