# R&D Engineering, Principal Engineer

**Company**: Synopsys
**Location**: Agrate Brianza
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Salary**: Competitive salaries
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/agrate-brianza/r-and-d-engineering-principal-engineer/44408/93988432736?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_715cdf02-c13

## Description

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a seasoned engineering leader with a passion for innovation and a deep understanding of physical design methodologies for cutting-edge semiconductor technologies. With a proven track record of successful project tape-outs, you thrive in collaborative, multidisciplinary environments, and you enjoy mentoring and guiding teams to achieve ambitious technical goals.

Your experience spans advanced FinFET nodes and the latest SERDES standards, and you possess a nuanced appreciation for both digital and mixed-signal architectures. You are methodology-driven, adept at software and scripting, and you have a strong grasp of CAD automation. Communication is your forte, whether you’re interfacing with peer groups, customers, or cross-functional teams.

Leading the physical implementation of advanced high-speed interface IPs and test-chips, from RTL to GDSII. Driving project execution for SERDES developments (56G/112G/224G PAM4/6) across multiple process nodes, including the latest FinFET technologies. Collaborating closely with front-end, analog, CAD, and product teams to ensure seamless integration and sign-off. Managing and mentoring a small team of engineers, fostering a culture of excellence, innovation, and continuous improvement. Developing and refining timing constraints and design architectures to ensure on-time delivery and optimal power/area targets. Applying advanced low-power design techniques and addressing the challenges of analog/digital interfaces in complex mixed-signal IPs. Contributing to methodology enhancements, CAD automation, and process improvement initiatives. Elevate Synopsys’ leadership in high-speed SERDES IP and mixed-signal solutions for next-generation silicon. Accelerate time-to-market for advanced interface IPs by ensuring robust and efficient physical implementation flows. Drive innovation in low-power and high-performance design, influencing industry standards and best practices. Mentor and empower engineering talent, building a high-performing team that delivers exceptional results. Strengthen cross-functional collaboration, optimizing integration and sign-off processes across technology domains. Enhance customer satisfaction through technical excellence, timely delivery, and superior product quality.

## Skills

### Required
- digital design
- physical design
- FinFET nodes
- SERDES standards
- CAD automation
- software and scripting
- timing constraints
- design architectures
- low-power design
- analog/digital interfaces

### Nice to have
- methodology-driven
- collaborative
- multidisciplinary
- technical leadership
- team management
- communication
- project execution
- integration and sign-off

---

Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/agrate-brianza/r-and-d-engineering-principal-engineer/44408/93988432736?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)