# R&D Engineering, Staff Engineer

**Company**: Synopsys
**Location**: Sunnyvale, California
**Experience**: staff
**Job type**: full-time
**Salary**: $138000-$207000
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/sunnyvale/r-and-d-engineering-staff-engineer/44408/102251697488?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_6fee2202-dfe

## Description

Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing.

You will work on Fusion Compiler, the tool that powers physical design for the most advanced chips in the world. The problems are real, the customers are demanding, and what you build will matter.

### Responsibilities

- Develop and enhance clock tree synthesis and clock optimization algorithms in Fusion Compiler, focusing on skew balancing, useful skew, buffering strategies, and insertion delay optimization

- Debug timing and clocking issues in customer designs across advanced process nodes (16nm to 5nm), identify root causes, and translate findings into product improvements

- Design and prototype new CTS and post-CTS optimization flows that integrate into customer methodologies and improve quality of results, runtime, and convergence predictability

- Collaborate directly with R&D engineers, Customer Application Engineers, and Account Consultants to understand real-world design challenges and align product direction with customer needs

- Implement and test new features in C++, Python, and Tcl, ensuring correctness, performance, and maintainability across large, complex codebases

- Analyze clock architecture tradeoffs including skew, latency, OCV-aware optimization, and uncertainty to drive better design outcomes across market verticals

- Contribute to continuous improvement of clock quality of results, addressing power, timing closure, and robustness across evolving process technologies

### Requirements

- Master's degree in Computer Science, Computer Engineering, Electronics Engineering, Mathematics, or related field with 2+ years of professional experience, or Ph.D. in a related field

- Strong proficiency in C++ for performance-critical algorithm development and systems software

- Experience with clock tree synthesis, static timing analysis, timing closure, or physical synthesis flows in an EDA or semiconductor design context

- Solid understanding of clock architecture concepts including skew, latency, insertion delay, transition, uncertainty, and OCV-aware optimization

- Familiarity with VLSI processes and physical design methodology, including timing, area, power, congestion, and signal integrity tradeoffs

- Working knowledge of Python and Tcl for scripting, automation, and tool integration

- Experience with advanced technology nodes (16nm to 5nm) is a plus, understanding the unique challenges of finFET and gate-all-around processes strengthens your ability to solve real customer problems

## Skills

### Required
- C++
- Python
- Tcl
- clock tree synthesis
- static timing analysis
- timing closure
- physical synthesis

### Nice to have
- experience with advanced technology nodes (16nm to 5nm)
- finFET and gate-all-around processes

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/sunnyvale/r-and-d-engineering-staff-engineer/44408/102251697488?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)