# Senior ASIC Verification Engineer

**Company**: NVIDIA
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Verification-Engineer---Clocks_JR2026417?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_6ccf9ac7-529

## Description

The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification.

The NVIDIA Clocks Team is committed to delivering high-quality clocking and reset logic to various units in SOC automotive and datacenter ASICs.

The complexity of the clocks and resets design has increased many folds, requiring sophisticated verification to deliver a bug-free clocks design to power our product lines ranging from Data Centers, Consumer graphics to Self-driving cars and the growing field of artificial intelligence.

**Responsibilities**

- Own validation of Clocking structures in Tegra automotive and datacenter products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix, and productization.

- Tackle sophisticated problems and develop a scalable solution that works across platforms.

- Hands-on experience with industry-standard tools and state-of-the-art verification methodologies, including coding in System Verilog, UVM, C++, Perl, Python, and NVIDIA custom compilers and tools.

- Partner closely with our clocks architecture and design team to validate our clocks design.

- Coordinate with internal and external teams across time zones.

**Requirements**

- BS or MS in EE/ECE or equivalent experience.

- 3+ years of relevant industry work experience.

- Good understanding of Logic Design and Architecture.

- Expertise in industry-standard verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.

- Exposure to block-level and system-level verification.

- Strong coding skills in System Verilog, scripting languages (Perl/Python), and C++.

- Ability to collaborate and work with multiple groups.

- Prior experience in implementing Test plans for pre-silicon platforms.

- Understanding of DFT/IST is optional.

## Skills

### Required
- System Verilog
- UVM
- C++
- Perl
- Python
- ASIC Verification
- Design Verification

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/India-Bengaluru/ASIC-Verification-Engineer---Clocks_JR2026417?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)