# Soc Engineer (synthesis/timing) -18607

**Company**: Synopsys
**Location**: Ho Chi Minh City
**Work arrangement**: onsite
**Experience**: mid
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/ho-chi-minh-city/soc-engineer-synthesis-timing-18607/44408/100750939712?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_6c1dceee-500

## Description

We are seeking a SOC engineer to work on ASIC/SOC projects at Synopsys in Ho Chi Minh City, District 7.

The successful candidate will be responsible for the development and implementation of System Design Solutions using Synopsys EDA tools and IP to solve customer problems as part of a service project team.

**Responsibilities and Duties**

- Synthesis

- LEC

- LDRC

- GCA

- STA

- PTPX

The engineer will contribute to both turnkey projects and act as a trusted advisor to customer design. They will develop innovative solutions to problems with little guidance and implement them independently. The engineer will set task-level goals and consistently meet schedules. They will work with other Synopsys teams, including BU AEs and Sales, to develop, broaden, and deploy Tool and IP solutions.

**Qualifications**

- 2-4 years of related experience

- Good understanding of ASIC/SOC design, synthesis, and timing closure

- Familiarity with Synthesis, LEC, STA flow

- Experience in low-power, high-performance design, and advanced nodes under 12nm is a plus

- Knowledge of RTL, DFT, LDRC, GCA, VCLP, PTPX, IREM is advantageous

- Familiarity with scripting languages such as TCL, Perl, Python

- Good English communication skills and willingness to work with customers

- BS or MS degree in EE or a related major

**Benefits**

- Comprehensive medical and healthcare plans

- Time away programs, including ETO and FTO

- Family support, including maternity and paternity leave, parenting resources, adoption, and surrogacy assistance

- ESPP: purchase Synopsys common stock at a 15% discount

- Retirement plans that vary by region and country

- Competitive salaries

## Skills

### Required
- ASIC/SOC design
- synthesis
- timing closure
- LEC
- STA flow
- RTL
- DFT
- LDRC
- GCA
- VCLP
- PTPX
- IREM
- TCL
- Perl
- Python

### Nice to have
- low-power design
- high-performance design
- advanced nodes under 12nm

---

Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/ho-chi-minh-city/soc-engineer-synthesis-timing-18607/44408/100750939712?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)