# ASIC Physical Design, Sr Staff Engineer

**Company**: Synopsys
**Location**: Ho Chi Minh City
**Work arrangement**: onsite
**Experience**: senior
**Job type**: employee
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-sr-staff-engineer/44408/94504529424?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_6b2f759f-9d4

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You take pride in solving the toughest physical design problems, the kind where advanced nodes, tight margins, and complex IP all collide. You're the one who spots timing issues before they're fire drills and who automates flows so the team can actually sleep before tape-out. If a tool throws a curveball, you debug and document, not just fix for yourself. You like working across teams,architecture, RTL, circuits,because you know every decision you make echoes downstream. You want your work to ship and matter. At Synopsys, you'll own the path from RTL to GDS and raise the bar for everyone around you.

Key responsibilities include:

- Owning and optimizing RTL-to-GDSII flow for UCIE IP, including STA and signoff (PrimeTime, IC Compiler II, ICV, RedHawk)

- Integrating covercells, macros, and IP, ensuring clean abutment and QA

- Automating tool flows, debugging issues, and documenting best practices

- Collaborating with architecture, RTL, and circuit teams on test chip development

- Preparing tape-out views, documentation, and managing foundry checklists

Impact you'll have:

- Deliver high-quality, high-performance UCIE IP that meets aggressive PPA goals

- Eliminate late-stage surprises through robust flows and early issue detection

- Save team time by automating repeatable tasks and sharing solutions

- Enable smooth integration for SoC teams and downstream users

- Raise technical standards and reliability across projects

## Skills

### Required
- RTL-to-GDSII flow
- STA and signoff
- PrimeTime
- IC Compiler II
- ICV
- RedHawk
- covercells
- macros
- IP
- scripting
- Tcl
- Python

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-sr-staff-engineer/44408/94504529424?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)