# Senior Staff RTL Design Engineer

**Company**: Synopsys
**Location**: Boxorough, Massachusetts
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Salary**: $138,000 - $208,000
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/boxborough/senior-staff-rtl-design-engineer-16908/44408/93816738832?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_6ad643d1-286

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

**Job Description**

- Design RTL modules for LPDDR PHY IP from microarchitecture through synthesis-ready implementation

- Optimize designs to meet timing, power, and area targets across multiple process nodes

- Develop Perl automation for design generation and flow integration

- Collaborate with cross-functional teams to resolve timing and power challenges

- Contribute to design reviews and methodology development

**The Impact You Will Have**

- Your designs will enable LPDDR PHY IP deployed in high-volume mobile, automotive, and AI products

- You will contribute to a major revenue-generating product line for Synopsys

- Your work will define performance characteristics for customer systems-on-chip

- Your automation will improve design efficiency across the engineering team

- Your expertise will influence architectural decisions for future products

**What You'll Need**

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

- 10+ years of ASIC digital design experience with RTL ownership in production silicon

- Expert Verilog proficiency for timing-critical designs

- Strong Perl scripting skills for design automation

- Deep knowledge of synthesis, timing analysis, and power optimization

- Experience with PHY IP or high-speed interfaces is preferred

**Who You Are**

- You understand how RTL structure affects timing and power outcomes

- You communicate effectively across technical disciplines

- You produce maintainable code that supports collaboration

- You identify process improvements proactively

- You resolve technical issues through systematic analysis

**The Team You'll Be Part Of**

You will join the team responsible for microarchitecture and front-end design of LPDDR PHY IP. This core product generates significant revenue and enables critical functionality in customer designs across mobile, automotive, and AI markets.

**Rewards and Benefits**

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

## Skills

### Required
- RTL design
- ASIC digital design
- Verilog
- Perl scripting
- Synthesis
- Timing analysis
- Power optimization

### Nice to have
- PHY IP
- High-speed interfaces

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/boxborough/senior-staff-rtl-design-engineer-16908/44408/93816738832?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)