# ASIC Design Engineer Technical Lead

**Company**: Cisco
**Location**: San Jose, California
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Salary**: $186,900.00 to $267,700.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2012543?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_6a4c5129-8a2

## Description

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms,like Silicon One,are shaping the technology industry.

As an ASIC Design Engineer Technical Lead, you will participate in and contribute to chip architecture definition and discussions. You will author design specifications and participate in micro-architecture specification reviews. You will implement Verilog RTL to meet timing and performance requirements. You will help define, evolve, and support our design methodology. You will mentor junior engineers on performing project tasks and problem solving. You will collaborate with the verification team to address design bugs and close code coverage. You will work closely with the physical design team to close design timing and place-and-route issues. You will triage, debug, and root cause simulation, software bring-up, and customer failures. You will perform diagnostic and post silicon validation tests in the lab.

Minimum qualifications include a Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or PhD in Electrical Engineering or Computer Engineering + 3 years in ASIC Design experience. You should have Verilog/System Verilog programming experience, interactive and waveform debug experience, experience delivering ASIC designs from specification to tape-out, and experience in architecture and micro architecture development.

Preferred qualifications include experience resolving setup and hold timing violations with RTL modification, scripting experience (Python, Perl, TCL, shell programming), demonstrated ability in troubleshooting and debugging, and good written and verbal communication skills.

The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation, equity, or benefits.

## Skills

### Required
- Verilog
- System Verilog
- ASIC Design
- Electrical Engineering
- Computer Engineering

### Nice to have
- Python
- Perl
- TCL
- shell programming
- troubleshooting
- debugging

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2012543?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)