# ASIC Physical Design, Sr Engineer

**Company**: Synopsys
**Location**: Bengaluru
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/bengaluru/asic-physical-design-sr-engineer/44408/93712504224
**Canonical**: https://yubhub.co/jobs/job_68de4e05-3af

## Description

We are seeking a highly skilled ASIC Physical Design Senior Engineer to join our team. As a key member of our team, you will be responsible for implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below). You will also perform timing closure for designs operating above ~4GHz, ensuring robust performance and reliability.

Your responsibilities will include:

Implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below). Performing timing closure for designs operating above ~4GHz, ensuring robust performance and reliability. Collaborating daily with local and US counterparts to align on technical challenges and project milestones. Integrating mixed-signal macro IPs and optimizing their placement within complex chip architectures. Designing and building efficient clock trees with exceptionally tight skew balancing to meet stringent requirements. Driving continuous improvement in implementation methodologies and sharing best practices across the team. Participating in design reviews, providing critical feedback and innovative solutions to enhance project outcomes.

As a senior engineer, you will have a strong technical foundation in ASIC physical design and hands-on experience with DDR IP implementation and timing closure, especially at advanced nodes (10nm, 7nm, 6nm and below). You will also have proficiency in EDA tools for synthesis, place-and-route, and timing analysis.

If you are a detail-oriented and analytical individual with a drive for technical excellence, effective communication skills, and a collaborative mindset, we encourage you to apply for this exciting opportunity.

## Skills

### Required
- ASIC physical design
- DDR IP implementation
- Timing closure
- EDA tools
- Synthesis
- Place-and-route
- Timing analysis

### Nice to have
- Clock tree synthesis
- Mixed-signal macro IPs
- Implementation methodologies