# Advanced Packaging Technologist

**Company**: OpenAI
**Location**: San Francisco
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Salary**: $266K – $445K
**Category**: Engineering
**Industry**: Technology
**Wikidata**: https://www.wikidata.org/wiki/Q124605186

**Apply**: https://jobs.ashbyhq.com/openai/4a2ed3a8-790d-470b-81fb-9e256cc87250
**Canonical**: https://yubhub.co/jobs/job_682966d5-14a

## Description

## Advanced Packaging Technologist

### About the Team:

OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

### Role Overview

We are seeking an experienced engineer to lead the development of advanced packaging technologies that enable next-generation, high-performance compute systems. This role sits at the intersection of chip architecture, package integration, and manufacturing scale-up, driving breakthroughs in performance, power, thermal, and reliability. The ideal candidate brings deep expertise in 2.5D and 3.5D large-reticle integration and Co-Packaged Optics (CPO) packaging, with a proven ability to translate advanced concepts into qualified, high-volume production solutions.

### In this role you will:

- Architect, develop, and prototype advanced packaging solutions (2.5D/3D integration, large-format interposers/bridges, high-density substrates, advanced assembly flows), and drive end-to-end qualification for high-volume production.

- Develop packaging concepts and requirements to support CPO packaging, including optical/electrical co-integration considerations, thermal/mechanical constraints, and high-volume manufacturability.

- Lead large-reticle and multi-die integration strategies, including mechanical/thermal co-design, warpage control, and yield/reliability risk mitigation across package scale-up.

- Identify and solve fundamental technical challenges in package architecture, integration, and manufacturability for high-performance compute chips.

- Collaborate closely with cross-functional teams (silicon architecture, SI/PI, thermal, mechanical, system, test, and manufacturing) to align package development with product requirements and program milestones.

- Drive vendor engagement and technical alignment with external partners (foundry/OSAT/material/tool vendors), including technology selection, DOE planning, and qualification readiness.

### You might thrive in this role if you have:

- Large-reticle / large-body-size integration, including interposer/bridge-based architectures, package-scale mechanical/thermal risk management, and manufacturability at scale.

- Hands-on experience with CPO packaging, including package-level optical integration constraints and cross-domain trade-offs (electrical/optical/thermal/mechanical).

- Proven track record developing and productizing large-format, high-power, high-speed advanced packaging technologies for high-performance compute products.

- In-depth expertise across advanced packaging techniques and platforms used in the semiconductor industry (2.5D, 3D stacking, interposers/bridges, high-density substrates, advanced materials and assembly).

- Strong understanding of chip–package co-design: how chip architecture, I/O, power delivery, and floorplan decisions interact with packaging architecture and constraints.

### Preferred Qualifications

- Solid understanding of thermal and mechanical interactions in large-format packages (warpage, stress, lid/heat-spreader/cold-plate interfaces, material interactions).

- Working knowledge of reliability requirements and qualification methodologies for advanced packages (JEDEC/industry practices, failure analysis, DOE-driven learning cycles).

- Familiarity with system-level considerations and chip architecture fundamentals (I/O topology, HBM/advanced memory integration, SI/PI constraints, module-to-system integration).

## Skills

### Required
- Advanced Packaging
- 2.5D and 3.5D large-reticle integration
- Co-Packaged Optics (CPO) packaging
- Chip–package co-design
- Thermal and mechanical interactions in large-format packages
- Reliability requirements and qualification methodologies for advanced packages

### Nice to have
- Large-reticle / large-body-size integration
- Hands-on experience with CPO packaging
- Proven track record developing and productizing large-format, high-power, high-speed advanced packaging technologies
- In-depth expertise across advanced packaging techniques and platforms used in the semiconductor industry