# Physical Design Engineer

**Company**: Cisco
**Location**: San Jose, California
**Experience**: senior
**Job type**: full-time
**Salary**: $125,700.00 - $203,100.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Physical-Design-Engineer-II--Full-Time-----United-States_2024671?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_67b9d11f-4f8

## Description

The Silicon One team at Cisco creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.

As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips.

Responsibilities:

- Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).

- Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.

- Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.

- Implement and manage timing ECO strategies using tools like Tweaker/ PrimeTime .

- Analyze quality and efficiency gaps, recommend tool , flow, and methodology improvements.

- Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency.

- Evaluate and implement new timing methodologies; provide creative debugging solutions.

- Contribute to best practices and drive methodology alignment across projects.

Minimum Qualifications:

- Meet one of the following (completed within the past 3 years or expected to be completed within the next 12 months):

- A Master's degree with 0 years of work experience; or

- A Bachelor's degree with 2 years of work experience.

- Qualifying education and work experience should be in ASIC Physical Design, ASIC design, engineering or a related field.

- Foundational knowledge of ASIC physical design and implementation flows gained through academic projects, internships, or relevant coursework.

- Understanding of physical design concepts, including floor planning , clock tree synthesis, power distribution, and I/O planning.

- Exposure to the physical design lifecycle, including logic synthesis, placement, routing, and basic timing closure.

Preferred Qualifications:

- Proficiency in scripting languages such as Python, Tcl , or Perl for task automation and data analysis.

- Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus , Synopsys ICC2, or Synopsys Design Compiler) through lab work or internships.

- Familiarity with physical verification processes (DRC/LVS) using tools such as Mentor Calibre or Synopsys ICV.

- Exposure to static timing analysis concepts and tools, such as PrimeTime .

Benefits:

- Medical, dental and vision insurance

- 401(k) plan with a Cisco matching contribution

- Paid parental leave

- Short and long-term disability coverage

- Basic life insurance

- Paid time away (10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees)

- Flexible vacation time off program

- 80 hours of sick time off provided on hire date and each January 1st thereafter

## Skills

### Required
- ASIC Physical Design
- ASIC design
- engineering
- Python
- Tcl
- Perl
- Cadence Innovus
- Synopsys ICC2
- Synopsys Design Compiler

### Nice to have
- static timing analysis
- PrimeTime
- Mentor Calibre
- Synopsys ICV

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Physical-Design-Engineer-II--Full-Time-----United-States_2024671?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)