# EDA flow and Logic Synthesis Engineer (Senior Engineer)

**Company**: Synopsys
**Location**: Dublin, Leinster
**Experience**: senior
**Job type**: employee
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/dublin/eda-flow-and-logic-synthesis-engineer-senior-engineer/44408/97142011104?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_67a6db23-ae8

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.

Within our HPC Controller IP organization, the mid-end team is the bridge between RTL design and physical implementation.

You are a motivated mid-end engineer with a solid grasp of ASIC design and verification flows, and genuine enthusiasm for automation, flow robustness, and using AI to raise engineering productivity, debug speed, and quality of results.

**What You'll Be Doing:**

- Develop, run, and support mid-end flows spanning synthesis, DFT, static checking (SpyGlass), formal equivalence, power analysis, and related quality gates.

- Convert RTL outputs into clean, constrained, implementation-ready inputs for physical design.

- Build and maintain Tcl-based automation, dashboards, and project infrastructure , and apply AI to accelerate the work (e.g., triaging flow logs, summarizing QoR trends, drafting and refactoring scripts).

- Debug flow failures end to end: analyze reports, isolate root cause, and drive issues to closure with design, verification, DFT, and implementation teams.

- Improve documentation, handoff criteria, and reusable collateral so execution stays consistent across IP programs.

**The Impact You Will Have:**

- Higher-quality RTL-to-physical-design handoffs and lower implementation risk.

- Faster, more scalable execution through stronger automation and AI-enabled analysis.

- Synthesis, DFT, static, formal, and power issues caught earlier in the cycle.

- Tighter collaboration across the RTL-to-implementation chain.

- Robust, implementation-ready soft IP shipped with clear constraints, checks, and release collateral.

**What You'll Need(Core):**

- Working knowledge of ASIC design, verification, and mid-end development flows, typically gained through 2+ years of relevant experience or equivalent project work.

- Hands-on synthesis experience, with the ability to analyze and resolve synthesis issues.

- Good Tcl scripting skills and a practical, automation-first mindset.

- Familiarity with some of the following: DFT concepts, static checking (SpyGlass or equivalent), formal equivalence (e.g., Formality), or power analysis , and willingness to grow across the rest.

- Ability to use AI tools effectively to accelerate debugging, summarize results, and improve scripts and flows.

- Good analytical, problem-solving, communication, and documentation skills.

- BS/MS in Electrical/Computer Engineering or equivalent experience.

**Rewards and Benefits:** We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

## Skills

### Required
- ASIC design
- verification flows
- synthesis
- DFT
- Tcl scripting
- AI tools
- analytical skills
- problem-solving skills
- communication skills
- documentation skills

### Nice to have
- IP development methodologies
- IP packaging
- reusable IP delivery
- Synopsys tools such as Fusion Compiler and VC SpyGlass

---

Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/dublin/eda-flow-and-logic-synthesis-engineer-senior-engineer/44408/97142011104?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)