# Physical Design Engineer

**Company**: Cisco
**Experience**: senior
**Job type**: full-time
**Salary**: $186,900.00 to $267,700.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2029332?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_646766e0-0f7

## Description

The Silicon One team at Cisco creates innovative hardware platforms central to the AI era, powering core Switching, Routing, and Wireless products for organizations globally.

As a Physical Design Engineer at Silicon One Optics, you will floorplan, tape out, and physically realize next-gen 800G, 1.6T, and multi-terabit optical transceivers and driver ICs.

Key responsibilities:

- Lead end-to-end RTL-to-GDSII physical design implementation across advanced nodes

- Architect and scale digital implementation flows using custom TCL/Python automation

- Lead physical execution across PnR, CTS, MMMC timing closure, and ECO iterations

Requirements:

- Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience

- Prior experience in ASIC/SoC physical design and implementation in advanced tech nodes

- Hands-on experience with EDA tool flows, back-end sign-off criteria, and workflow automation using Python, TCL, and Shell scripts

Preferred qualifications:

- Experience in closing designs with high-speed, high-density, macro-dominant, and I/O cell–intensive blocks

- Experience in STA methodology, SDC timing constraint creation, analysis, and timing ECO generation

- Hands-on experience with functional equivalence checking and functional ECOs

Benefits:

- Medical, dental, and vision insurance

- 401(k) plan with Cisco matching contribution

- Paid parental leave, short and long-term disability coverage, and basic life insurance

- Paid time away, including holidays, vacation time, and sick time

- Opportunities for career growth and professional development

## Skills

### Required
- physical design
- ASIC/SoC
- EDA tool flows
- Python
- TCL
- Shell scripts

### Nice to have
- STA methodology
- SDC timing constraint creation
- functional equivalence checking
- power grid design

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2029332?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)