# ASIC Design Engineer

**Company**: Hewlett Packard Enterprise
**Location**: Bengaluru, Karnātaka
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Bengaluru-Karntaka-India/ASIC-Design-Engineer_1208243-2?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_61bf0cc9-e27

## Description

We are seeking a skilled ASIC Design Engineer to join our team. As an ASIC Design Engineer, you will be responsible for designing and architecting high-performance blocks for advanced networking ASICs. You will work closely with system design teams across geographies and have the opportunity to interact with various stakeholders.

Responsibilities:

- Define and architect high-performance blocks for the latest, most advanced networking ASICs

- Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power

- Collaborate with the verification team in the development of the testplan and assist in debugging test failures

- Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes

Requirements:

- Strong Verilog RTL coding skills

- Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable

- Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus

- Knowledge of high-performance memory subsystems

- Knowledge of multi-domain clock synchronization and high-speed serial interfaces

- Strong problem-solving and ASIC debugging skills

- Excellent written and verbal communication skills

- MSEE or BSEE is required with 5+ years of experience

Benefits:

- Comprehensive suite of benefits that support physical, financial, and emotional wellbeing

- Investment in career development and growth

- Unconditional inclusion and celebration of individual uniqueness

## Skills

### Required
- Verilog RTL
- Synopsys Design Compiler
- Verplex LEC
- Spyglass
- ASIC design
- Networking protocols
- High-performance memory subsystems
- Multi-domain clock synchronization
- High-speed serial interfaces

### Nice to have
- Experience designing ASICs for networking protocols (Ethernet, FCoE)

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Source: [Apply at hpe.wd5.myworkdayjobs.com](https://hpe.wd5.myworkdayjobs.com/en-US/Jobsathpe/job/Bengaluru-Karntaka-India/ASIC-Design-Engineer_1208243-2?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)