# Front-End ASIC Digital Design, Sr. Staff Engineer

**Company**: Synopsys
**Location**: Austin, Texas
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Salary**: $138000-$208000
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/austin/front-end-asic-digital-design-sr-staff-engineer-18423/44408/101009735120?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_6051e103-9bb

## Description

We are seeking a Front-End ASIC Design Engineer with hands-on experience taking RTL from specification through design sign-off. You will own RTL blocks for high-performance SoCs, drive synthesis and timing closure quality at the front-end boundary, and ensure designs are clean against lint, CDC/RDC, timing, and power sign-off criteria before hand-off to physical design.

Responsibilities:

- Drive front-end sign-off: static timing analysis (STA), lint, CDC/RDC, synthesis, and power efficient design.

- Translate architectural specifications and micro-architecture documents into synthesizable RTL (SystemVerilog/Verilog) for blocks and subsystems.

- Own timing constraint (SDC) development and review; support full-chip timing closure.

- Perform synthesis, QoR analysis, and iterative RTL optimization for area, timing, congestion, and power.

- Apply formal property verification (VC Formal) and assertion-based design (SVA) to validate block behavior.

- Run power estimation and analysis (PrimePower) and feed findings back into RTL optimization.

- Contribute to methodology improvement, scripting, and regression automation.

Requirements:

- BS/MS in Electrical/Computer Engineering or a related field, with 8+ years of experience in ASIC design and STA sign-off.

- Demonstrated experience with front-end sign-off flows: STA (PrimeTime), lint (SpyGlass), and CDC/RDC.

- Strong proficiency in SystemVerilog/Verilog RTL coding for synthesis.

- Solid understanding of synthesis (Design Compiler / Fusion Compiler) and QoR analysis.

- Experience with low-power design techniques: clock gating, power gating, multi-Vt, UPF.

- Working knowledge of SDC constraint development and timing closure methodology.

- Proficiency in scripting: TCL, Python, Perl, and Linux/UNIX environments.

- Command of digital design fundamentals: FSMs, arbitration, clock domain crossing, memory interfaces, and standard protocols (AMBA AXI/AHB/APB).

- High-speed interface IP integration experience (PCIe, DDR/LPDDR, Ethernet, USB, MIPI).

Benefits:

- Comprehensive medical and healthcare plans that work for you and your family.

- In addition to company holidays, we have ETO and FTO Programs.

- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

- Save for your future with our retirement plans that vary by region and country.

- Competitive salaries.

## Skills

### Required
- ASIC design
- STA sign-off
- SystemVerilog/Verilog
- synthesis
- QoR analysis
- low-power design techniques
- SDC constraint development
- timing closure methodology
- scripting
- digital design fundamentals
- high-speed interface IP integration

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/austin/front-end-asic-digital-design-sr-staff-engineer-18423/44408/101009735120?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)