# Principal Physical Design Engineer – SerDes

**Company**: Synopsys
**Location**: Mississauga
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/mississauga/principal-physical-design-engineer-serdes-16976/44408/94087525936
**Canonical**: https://yubhub.co/jobs/job_5dc3ce00-3cc

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

We are seeking a Principal Physical Design Engineer to lead the physical implementation of high-speed interface IPs and test-chips, taking designs from RTL to GDSII. The ideal candidate will have intimate knowledge of the full design cycle from RTL to GDSII, including chip-level implementation, and experience with advanced FinFET nodes (TSMC 16nm or below) and low-power design techniques.

The successful candidate will be responsible for driving timing and physical sign-off processes to ensure optimal performance and reliability, collaborating with front-end, analog, CAD, and product teams to solve complex mixed-signal integration challenges, and guiding a team of engineers through project execution, mentoring and developing talent within the group.

Key responsibilities include:

- Leading the physical implementation of high-speed interface IPs and test-chips, taking designs from RTL to GDSII

- Driving timing and physical sign-off processes to ensure optimal performance and reliability

- Collaborating with front-end, analog, CAD, and product teams to solve complex mixed-signal integration challenges

- Guiding a team of engineers through project execution, mentoring and developing talent within the group

The ideal candidate will have 12+ years of digital or physical design experience with recent project tape-outs as a technical driver or project lead, intimate knowledge of the full design cycle from RTL to GDSII, including chip-level implementation, and experience with advanced FinFET nodes (TSMC 16nm or below) and low-power design techniques.

In addition to technical expertise, the successful candidate will be a collaborative and communicative leader, able to work effectively across diverse teams, autonomous and decisive, comfortable managing multiple priorities and interruptions, and methodology-driven, with a passion for continuous improvement and innovation.

## Skills

### Required
- digital design
- physical design
- high-speed interface IPs
- test-chips
- RTL to GDSII
- advanced FinFET nodes
- low-power design techniques
- timing and physical sign-off processes
- mixed-signal integration challenges
- project execution
- team leadership
- mentoring and talent development