# SOC Engineering, Senior Engineer

**Company**: Synopsys
**Location**: Sunnyvale, California
**Experience**: senior
**Job type**: employee
**Salary**: $112000-$169000
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/sunnyvale/soc-engineering-senior-engineer/44408/100962190512?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_5cf7f40e-71b

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent the last few years deep in RTL code, turning specifications into working digital logic that actually synthesizes and meets timing. Good design is not just about functionality for you. It is about creating clean, robust RTL that enables efficient verification and predictable implementation.

### Responsibilities

- Write and review Verilog, SystemVerilog, or VHDL RTL for block-level designs including state machines, pipelines, FIFOs, and memory controllers based on micro-architecture specifications

- Run RTL quality checks using tools like linting, CDC/RDC analysis, and synthesis to ensure your design is clean before handoff to physical design

- Collaborate with verification engineers to debug testbench failures, refine corner cases, and close coverage gaps

- Work with physical design teams to resolve timing issues, optimize logic for synthesis, and support timing closure from netlist through signoff

- Implement standard interface protocols including AXI, APB, AHB, I2C, and SPI within SoC subsystems

- Use scripting in Python, Tcl, or shell to automate repetitive tasks in the design flow and improve team productivity

- Participate in design reviews with cross-functional teams across the globe, clearly communicating design decisions and tradeoffs

### The Impact You Will Have

- Contribute RTL blocks that achieve timing, area, and power targets while minimizing design iterations

- Deliver full SoC designs that ship in products for automotive, aerospace, defense, and high-performance computing customers

- Improve design quality and reduce downstream debug time by catching issues early through disciplined use of lint, CDC, and synthesis checks

- Enable faster project ramp by writing clear design documentation and participating in knowledge transfer across global teams

- Help refine internal design flows and methodologies by identifying bottlenecks and proposing automation or process improvements

- Support customer-specific design requirements by translating high-level specs into implementable RTL that meets project constraints

- Build reusable IP blocks and design patterns that accelerate future projects across the Solutions group

### Requirements

- Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

- 3 to 4 years of hands-on experience in ASIC or FPGA RTL design, implementation, and debug

- Strong proficiency in Verilog, SystemVerilog, or VHDL RTL coding for registers, pipelines, state machines, memories, and FIFOs

- Working knowledge of the ASIC design flow from micro-architecture through RTL development, synthesis, and timing closure

- Experience using industry-standard tools such as simulators, lint checkers, CDC/RDC analysis tools, synthesis tools, and static timing analysis

- Solid understanding of standard interface protocols including AXI, APB, AHB, I2C, and SPI

- Experience with more complex protocols like PCIe, DDR, or Ethernet is a plus, as is familiarity with SystemVerilog assertions, C++, or Python for verification or scripting tasks, low-power design methodologies and UPF, DFT requirements, Git-based development flows, formal verification tools, or AI-assisted engineering tools and code-generation assistants

### Benefits

- Comprehensive medical and healthcare plans that work for you and your family

- Time away programs including ETO and FTO

- Family support including maternity and paternity leave, parenting resources, adoption and surrogacy assistance

- ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back

- Retirement plans that vary by region and country

- Competitive salaries

## Skills

### Required
- ASIC/FPGA RTL design
- Verilog/SystemVerilog/VHDL
- RTL coding
- ASIC design flow
- linting
- CDC/RDC analysis
- synthesis
- static timing analysis
- AXI/APB/AHB/I2C/SPI

### Nice to have
- PCIe
- DDR
- Ethernet
- SystemVerilog assertions
- C++
- Python
- low-power design methodologies
- UPF
- DFT requirements
- Git-based development flows
- formal verification tools
- AI-assisted engineering tools

---

Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/sunnyvale/soc-engineering-senior-engineer/44408/100962190512?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)