# Memory Layout Design Engineer, Staff **Company**: Synopsys **Location**: Noida, Uttar Pradesh **Experience**: staff **Job type**: employee **Category**: Engineering **Industry**: Technology **Ticker**: SNPS **Wikidata**: https://www.wikidata.org/wiki/Q2303478 **Apply**: https://careers.synopsys.com/job/noida/memory-layout-design-engineer-staff/44408/97791386336?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply **Canonical**: https://yubhub.co/jobs/job_5c93a19a-eb0 ## Description ## Memory Layout Design Engineer, Staff Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. You have spent years deep in the details of custom memory layout, and you know that the difference between a memory compiler that ships and one that stalls out is usually in how you handled density, matching, and DRC closure three weeks before tape-out. At Synopsys, you will work on memory IP that powers chips across the industry. The work is technical, the problems are real, and what you design will ship. ### What You'll Be Doing - Design and own custom layouts for SRAM, Register Files, ROM, and related memory compiler IP blocks from floorplan through final signoff - Execute and close DRC, LVS, ERC, antenna, density, and reliability checks using Virtuoso and physical verification tools - Drive technology node migrations for memory compilers, resolving layout and verification issues that emerge with new process rules - Collaborate directly with circuit designers to ensure schematic-layout correlation, device matching, symmetry, and design intent are preserved - Develop and refine layout methodologies, automation scripts in Tcl, Perl, or Python, and best practices that improve team efficiency and design quality - Review layouts created by junior engineers, provide technical guidance, and mentor on complex layout challenges - Support customer-specific memory customization projects, working through optimization requests and delivering production-ready IP ### The Impact You Will Have - Your layouts will directly enable memory IP that ships in high-volume semiconductor products across automotive, mobile, AI, and data center applications - You will reduce design cycle time by improving layout automation and methodology, allowing the team to take on more projects with higher quality - Your ability to close complex DRC and LVS issues independently will unblock project milestones and keep compiler development on schedule - You will raise the technical bar for the team by mentoring junior designers and establishing layout standards that scale across technology nodes - Your collaboration with circuit and CAD teams will surface layout-driven insights that influence architecture and tool development decisions - You will help Synopsys deliver memory IP that meets the most demanding area, performance, power, and reliability requirements from leading semiconductor companies - Your work on technology migrations will position the memory IP portfolio for next-generation nodes and maintain Synopsys leadership in the market ### What You'll Need - Bachelor's or Master's degree in Electronics, VLSI, Microelectronics, or a related technical field - 8 to 10 years of hands-on experience in custom memory layout design, specifically SRAM, Register Files, ROM, or memory compiler development - Strong proficiency with custom layout tools such as Cadence Virtuoso or equivalent platforms - Demonstrated expertise in DRC/LVS closure, device matching and symmetry, and analog/custom layout techniques - Deep understanding of CMOS layout fundamentals, memory architecture, and FinFET technology nodes - Experience with parasitic extraction and physical verification flows, and the ability to interpret and act on results - Familiarity with scripting in Tcl, Perl, or Python for layout automation is a strong plus ### Who You Are - You can debug a complex LVS mismatch by tracing through netlists, schematics, and layout views without needing someone to walk you through it - You know when to optimize for area and when to prioritize matching or performance, and you can explain the trade-off to a circuit designer in a way that moves the decision forward - You review a junior engineer's layout and give feedback that is specific, actionable, and grounded in what will actually cause problems downstream - You work across teams with circuit designers, methodology engineers, and CAD without losing sight of what you are trying to deliver or when it needs to be done - You stay current on process technology changes and layout challenges that come with new nodes, and you bring that knowledge into your daily work - You take ownership of your projects and deliver milestones with limited supervision, raising issues early when dependencies or risks emerge ### Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. - Comprehensive medical and healthcare plans that work for you and your family - In addition to company holidays, we have ETO and FTO Programs - Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more - Purchase Synopsys common stock at a 15% discount, with a 24-month look-back - Save for your future with our retirement plans that vary by region and country - Competitive salaries ## Skills ### Required - custom memory layout design - SRAM - Register Files - ROM - memory compiler development - Cadence Virtuoso - DRC/LVS closure - device matching and symmetry - analog/custom layout techniques - CMOS layout fundamentals - memory architecture - FinFET technology nodes - parasitic extraction - physical verification flows ### Nice to have - scripting in Tcl - Perl - Python for layout automation --- Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/noida/memory-layout-design-engineer-staff/44408/97791386336?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)