# Senior Physical Design Methodology Engineer, PPA Fusion Compiler

**Company**: NVIDIA
**Location**: Santa Clara
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Physical-Design-Methodology-Engineer--PPA-Fusion-Compiler_JR2011273?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_5b3dea06-5e2

## Description

We're looking for a best-in-class Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join our outstanding Networking Silicon engineering team. You will develop efficient physical design methodologies for implementation of graphics processors and SOCs. Your key responsibilities will include developing unique and creative solutions to state-of-the-art physical design problems to improve PPA, formulating and developing ML-based solutions, and participating in developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power and noise analysis and back-end verification across multiple projects.

You will work on data-based analysis and algorithmic solutions for PPA check and improvement. We need someone with a strong background in physical design, including floor planning, clock and power distribution, place and route, integration and verification. You should also have knowledge of hierarchical design approach, top-down design, budgeting, timing and physical convergence, and experience with various process-related design issues including design for yield and manufacturability, EM and IR closure and thermal management.

As a Senior Physical Design Methodology Engineer, you will be eligible for equity and benefits. Applications for this job will be accepted at least until May 8, 2026.

## Skills

### Required
- Physical Design Engineering
- ML-based solution development
- Floor planning
- Clock and power distribution
- Place and route
- Integration and verification
- Hierarchical design approach
- Top-down design
- Budgeting
- Timing and physical convergence
- Design for yield and manufacturability
- EM and IR closure and thermal management

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Physical-Design-Methodology-Engineer--PPA-Fusion-Compiler_JR2011273?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)