# Semiconductor Packaging Component Quality Engineer

**Company**: Cisco
**Location**: San Jose, California
**Experience**: senior
**Job type**: full-time
**Salary**: $154,900.00 to $225,300.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/Semiconductor-Test-Engineer_2011748-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_58629ce9-0a1

## Description

The Component Quality and Technology (CQT) organization at Cisco is seeking a Semiconductor Packaging Component Quality Engineer to ensure the highest standards of component integrity.

You will use your deep packaging and board-level expertise to evaluate the quality, reliability, and physical integrity of packaged semiconductor components.

**Responsibilities**

- Assess and lead the quality and physical integrity of incoming packaged components from external suppliers.

- Review supplier-provided data or execute BLR/L2 reliability testing to ensure component-to-board interconnect integrity for best outcomes in SMT manufacturing and long-term field use.

- Oversee root-cause analysis on component failures, identifying package-level defects such as delamination, wire bond lifts, die cracking, and solder joint fatigue.

- Partner with external component suppliers and OSATs to audit packaging processes, review manufacturing reliability data, and resolve package-level reliability excursions.

- Evaluate supplier-driven package process changes (PCNs) and determine alignment with internal quality standards.

**Minimum Qualifications**

- Bachelor’s degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related field.

- 4+ years of experience in semiconductor quality, packaging reliability, or board-level failure analysis.

- Strong understanding of standard IC packaging types (e.g., BGA, QFN, WLCSP, Flip-Chip) and their associated material, mechanical, and thermal stress behaviors.

- Strong working knowledge of JEDEC and IPC standards regarding packaging, reliability testing, and board-level qualifications.

**Preferred Qualifications**

- Direct experience designing, setting up, and executing Level 2 (L2) / Board Level Reliability (BLR) testing pipelines, including thermal cycling, mechanical shock/drop testing, board flex testing, and continuous daisy-chain resistance monitoring.

- Proficiency with reliability software (e.g. Reliasoft, Weibull++, Minitab or JMP) and CAD/PCB layout viewers (e.g. Allegro, Altium).

- Familiarity with PCB board design principles, footprint layout constraints, and schematic routing that impact package solder joint reliability.

- Formal training in structured problem-solving methodologies (e.g., 8D, 5-Why, Fishbone analysis, Six Sigma Green/Black Belt).

**Benefits**

- Medical, dental and vision insurance

- 401(k) plan with a Cisco matching contribution

- Paid parental leave

- Short and long-term disability coverage

- Basic life insurance

- Paid time away (vacation, holidays, sick time)

- Optional 10 paid days per full calendar year to volunteer

## Skills

### Required
- Electrical Engineering
- Mechanical Engineering
- Materials Science
- JEDEC
- IPC
- BGA
- QFN
- WLCSP
- Flip-Chip

### Nice to have
- Reliasoft
- Weibull++
- Minitab
- JMP
- Allegro
- Altium
- Six Sigma Green/Black Belt

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/Semiconductor-Test-Engineer_2011748-1?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)