# ASIC Design Verification Engineer

**Company**: Cisco
**Location**: San Jose, CA
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Salary**: $155,000.00 to $222,600.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Design-Verification-Engineer_2027581?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_5719e8b7-dcc

## Description

The Silicon One team at Cisco is looking for an ASIC Design Verification Engineer to play a critical role in developing Cisco’s revolutionary data center solutions. You will architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips.

Responsibilities:

- Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure.

- Build DV environments from scratch for block and cluster levels.

- Develop, implement, and enhance test plans and tests for block and cluster verification, using both constraint-random and directed stimulus.

- Ensure comprehensive verification coverage through code and functional coverage implementation and review.

- Qualify RTL design by running Gate Level Simulations on netlists.

- Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration.

- Support design testing in emulation environments.

Minimum Qualifications:

- Bachelors degree in Computer, Electrical or Electronics Engineering, + 5 years of relevant technical experience, or Masters degree in a related field + 3 years of relevant technical experience, focused on ASIC design and verification.

- Experience in System Verilog or UVM methodology.

- Experience building reusable and scalable test benches from scratch.

- Experience with scripting using Perl and/or Python.

Preferred Qualifications:

- Experience with forwarding logic, parsers, or P4.

- Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS.

- Knowledge of formal verification tools (e.g., IEV or VC Formal).

- Domain knowledge in one or more protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.

Benefits:

- Medical, dental and vision insurance

- 401(k) plan with a Cisco matching contribution

- Paid parental leave

- Short and long-term disability coverage

- Basic life insurance

- Paid time away (10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees)

- Flexible vacation time off program

- 80 hours of sick time off provided on hire date and each January 1st thereafter

- Optional 10 paid days per full calendar year to volunteer

## Skills

### Required
- System Verilog
- UVM methodology
- Perl
- Python
- ASIC design and verification

### Nice to have
- forwarding logic
- parsers
- P4
- emulation platforms
- formal verification tools
- PCIe
- CXL
- Ethernet
- RDMA
- DDR
- TCP

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/ASIC-Design-Verification-Engineer_2027581?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)