# ASIC Verification Engineer, Sr Staff

**Company**: Synopsys
**Location**: Ho Chi Minh City
**Work arrangement**: onsite
**Experience**: senior
**Job type**: full-time
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/ho-chi-minh-city/asic-verification-engineer-sr-staff/44408/92669904832?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_55be5bf5-837

## Description

We are seeking a passionate and experienced ASIC Digital Design Engineer with a strong background in design verification to join our Digital and Verification Development team. As a key member of the team, you will be responsible for working on the development and validation of complex digital mixed signals for high-speed interface IP. Your expertise will be complemented by your ability to communicate effectively and work well within a team.

Key responsibilities include:

- Planning tests, checklists, coverage, and assertion planning

- Creating detailed verification environments from functional specifications

- Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification

- Writing test cases, checkers, and coverage that implement the verification test plan

- Debugging simulations, including those of real signals modeled using SystemVerilog for analog

- Performing RTL, GLS, and co-simulations and ensuring coverage closure

- Participating in technical reviews and contributing actively

- Providing customer support with the bring-up of IP in customer simulation environments

- Following and improving development processes to ensure high-quality output

Requirements include:

- BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications

- 7+ years of experience in design verification

- Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal)

- Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus

- Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus

As a highly responsible and result-oriented individual with excellent English communication skills, both verbal and written, you will be a great team player, willing to support others. Self-motivated and highly enthusiastic about technology and solving problems, you will thrive in a collaborative environment.

## Skills

### Required
- VCS/Verdi simulation tools
- Formal verification tools (vc_formal)
- UPF
- UVM (Universal Verification Methodology)
- SVA (SystemVerilog Assertion)
- Perl/TCL/Python scripting

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/ho-chi-minh-city/asic-verification-engineer-sr-staff/44408/92669904832?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)