# ASIC Design Engineer

**Company**: NVIDIA
**Location**: Santa Clara, CA
**Work arrangement**: onsite
**Experience**: mid
**Job type**: full-time
**Salary**: Competitive salaries and a comprehensive benefits package
**Category**: Engineering
**Industry**: Technology

**Apply**: https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Design-Engineer_JR2019466?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_54c63c02-183

## Description

Apply for an ASIC Design Engineer position at NVIDIA.

We're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world.

As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work.

**What you'll be doing:**

Work on the cutting-edge standard cell libraries and/or custom ROM (Read Only Memory) modules in deep submicron technologies.

Drive the concepts of the transistor level standard cell circuit design, modeling, and performance analysis process.

Lead the function and feasibility verification of new ROM designs and set up new design flows.

Provide creative insights to support and enhance existing tools and flows and develop new simulations to perform design margin evaluations.

Collaborate with multi-functional teams regarding opportunities to improve standard cell development.

**What we need to see:**

MS in Electrical or Computer Engineering (or equivalent experience).

3+ years of experience.

Strong background in advanced submicron process issues.

Deep understanding of the build and verification of both conventional cell libraries and custom ROMs.

Hands-on experience running SPICE simulation, and capability to adapt to new simulation tools.

Experience with running EM/IR, aging, noise, margin, and high sigma variation simulations.

Hands-on experience of DRC/LVS debug.

Experience of designing and optimizing flip flops, level shifters, latches, and/or custom ROMs, register files, SRAM.

Strong proficiency in scripting language, such as, Perl, Tcl, Make, and automation methods/algorithms a certain plus.

**Ways to stand out from the crowd:**

Exposure to standard cell, memory, or custom circuit development would be beneficial.

Experience with RTL, logic synthesis, and familiarity with place and route is preferred.

Prior leadership experience is advantageous.

Good interpersonal skills, quick learner, proactive, innovative, highly motivated, and committed.

## Skills

### Required
- SPICE simulation
- Perl
- Tcl
- Make
- DRC/LVS debug
- EM/IR
- aging
- noise
- margin
- high sigma variation simulations
- flip flops
- level shifters
- latches
- custom ROMs
- register files
- SRAM

### Nice to have
- RTL
- logic synthesis
- place and route

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Source: [Apply at nvidia.wd5.myworkdayjobs.com](https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/ASIC-Design-Engineer_JR2019466?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)