# Hardware Engineer - Test Planning and Development

**Company**: Cisco
**Location**: San Jose, CA
**Work arrangement**: hybrid
**Experience**: senior
**Job type**: full-time
**Salary**: $167,700.00 to $245,200.00
**Category**: Engineering
**Industry**: Technology

**Apply**: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/Senior-ASIC-DFT-DV-Engineer--Hybrid-_2027721?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_548367b1-897

## Description

The Silicon One team at Cisco creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.

As a Hardware Engineer - Test Planning and Development, you will be responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design.

Key responsibilities:

- Collaborate with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation and post silicon validation flows.

- Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.

- Craft solutions and debug efficiently.

Minimum qualifications:

- Bachelor’s in Electrical Engineering or equivalent with at least 7+ years (or Master's with 4+ years) of experience.

- Prior experience in test planning based on complex design specifications.

- Prior experience in testbench development using System Verilog.

- Experience debugging using DVE/Verdi.

- Experience with TCL, Python or Perl.

Preferred qualifications:

- UVM and advanced System Verilog knowledge.

- Knowledge about JTAG protocol, scan architecture, MBIST and boundary scan.

The role offers a salary range of $167,700.00 to $245,200.00 and benefits, including medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance.

## Skills

### Required
- Electrical Engineering
- System Verilog
- TCL
- Python
- Perl
- DVE/Verdi

### Nice to have
- UVM
- JTAG protocol
- scan architecture
- MBIST
- boundary scan

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Source: [Apply at cisco.wd5.myworkdayjobs.com](https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/Senior-ASIC-DFT-DV-Engineer--Hybrid-_2027721?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)