# Layout Design, Staff Engineer

**Company**: Synopsys
**Location**: Yerevan
**Experience**: senior
**Job type**: employee
**Category**: Engineering
**Industry**: Technology
**Ticker**: SNPS
**Wikidata**: https://www.wikidata.org/wiki/Q2303478

**Apply**: https://careers.synopsys.com/job/porto-salvo/serdes-system-architecture-engineer/44408/94212498400?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply
**Canonical**: https://yubhub.co/jobs/job_540d895a-72e

## Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You know layout is not just about DRC rules; it is about understanding silicon physics and downstream impact on timing. You catch routing congestion or IR drop problems before they become blockers. You do not need a perfect floorplan. You ask the right questions and figure out the cleanest path forward. When a junior engineer hits a wall, you show them the fix and the thinking behind it. You write scripts because manual tasks should not exist.

### Responsibilities

- Design physical layout for complex IC blocks, balancing area, performance, power, and manufacturability

- Develop automation scripts in Shell, Tcl, and Python to streamline workflows

- Solve layout problems including routing congestion, power integrity, and design rule violations

- Manage layout projects from floorplanning through signoff

- Mentor junior engineers and review their work

### The Impact You Will Have

- Your layout decisions influence chip performance and manufacturability for Synopsys customers

- The scripts you build eliminate hours of manual work per project

- Your ability to catch issues early prevents costly respins

- Your mentorship builds a stronger layout team

- The methodologies you define shape how the team approaches future designs

### Requirements

- Masters in electrical engineering or equivalent

- 5+ years of IC layout design experience including floorplanning, placement, routing, and verification

- Advanced proficiency in Shell, Tcl, and Python

- Strong understanding of layout methodologies, DRC/LVS verification, and signoff flows

- Experience managing layout projects end to end

- Strong English communication skills

### Benefits

- Comprehensive medical and healthcare plans

- Time away programs including ETO and FTO

- Family support including maternity and paternity leave

- ESPP with a 15% discount on Synopsys common stock

- Retirement plans varying by region and country

- Competitive salaries

## Skills

### Required
- IC layout design
- Shell
- Tcl
- Python
- Electrical engineering

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Source: [Apply at careers.synopsys.com](https://careers.synopsys.com/job/porto-salvo/serdes-system-architecture-engineer/44408/94212498400?utm_source=yubhub.co&utm_medium=jobs_feed&utm_campaign=apply)